Abstract: Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: An image forming apparatus includes a communication interface unit to communicate with a network using a physical layer protocol (PHY), a first control unit that includes a first Media Access Controller (MAC) to perform Media Access Control for the PHY when the image forming apparatus operates in a normal mode, and to control the image forming apparatus, a second control unit that includes a second Media Access Controller (MAC) to perform Media Access Control for the PHY when the image forming apparatus operates in a power saving mode, and a switching unit to switch a data path between the PHY, the first MAC, and the second MAC according to the operation mode of the image forming apparatus.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.

Abstract: A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan clock input terminal, a logical circuit that performs a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generates an update clock and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holds the data or the scan data provided from the update input terminal when the update clock is provided.

Abstract: A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal.

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract: The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may also have a second switching array, which emits an output signal, which when the first signal first has changed its state, changes its state in reaction to a change in the state of the first signal, and, when the second signal first has changed its state, changes its state in reaction to a change in the state of the first signal.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A variable circuit for constructing a desired counter by changing the circuit configuration of the connection status of a plurality of flipflops. The flipflops may be arranged in first and second rows, or stages, whereby the flipflops of the first and second rows are interconnected.

Abstract: A semiconductor integrated circuit of the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.

Abstract: A programmable logic circuit is provided that solves glitch problems associated with asynchronous logic operations associated with conventional look-up tables by utilizing a preset dominant transparent latch element to replace a conventional look-up table. Since latch elements are normally present in programmable logic circuits (e.g., FPGAs) no additional circuitry is necessary to implement the approach of the present invention. In one exemplary embodiment, an FPGA is provided which includes an array of programmable latch elements, and an array of programmable flip-flop elements generating flip-flop output signals. One or more of the latch elements are programmed to form a preset dominant transparent latch (PDTL) such that the data signals are coupled to the data inputs and preset inputs of the latch. In this manner, the latch operates to replace conventional look-up tables by operating as a primitive OR or NOR gate to generate a desired output.

Abstract: A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((Clk×P)+O1)}.

Abstract: A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Abstract: A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is above the first predetermined level. The output register is active when the level of the clock pulse signal is above a second predetermined level and inactive when the clock pulse signal is below the second predetermined level. There exists a well-defined voltage range during which both the input and output registers are inactive. The transfer of information from the input register to the output register only occurs during the transition from a logic 0 level to a logic 1 level clock pulse signal. The SET and RESET inputs are only enabled when the clock pulse signal is at a logic 0 level.

Abstract: This invention relates to a J-K flip-flop circuit which achieves a decrease in area required on an integrated circuit and a reduction of cost. Three N-MOSFETs, whose gates respectively receive a clock CL1, a J signal, and a signal from one node of a second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to one node of a first flip-flop circuit. Three N-MOSFETs, whose gates respectively receive the clock CL1, a K signal, and a signal from the other node of the second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the first flip-flop circuit. Two N-MOSFETs, whose gates respectively receive a clock CL2 and a signal from one node of the first flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the second flip-flop circuit.