Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a first data input and to a second data input. The first data input is introduced into the feedback loop at a first set of points, and the second data input is introduced into the feedback loop at a second set of points.

Abstract: In a high voltage switch circuit for programming memory cells, preset devices for precharging the core circuit are eliminated by statically presetting nodes of the switch core circuit through a pair of drive circuits arranged to pull up or down a pair of cascoded transistors in the core circuit.

Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Abstract: A method and apparatus for reducing soft errors in which the method includes: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals coupled to the storage circuit, where evaluating the plurality of signals enables a first node to change from its predetermined state; and actively maintaining a second node in its predetermined state, where actively maintaining the predetermined state reduces the storage circuit's susceptibility to soft errors.

Abstract: A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.

Abstract: A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

Abstract: An integrated circuit includes at least one latch circuit (300). The latch circuit (300) includes a first stage comprising a latch node (311) positioned between a first pull up device (303) operable to receive a first data signal and a first pull down device (302) operative to receive second data signal. A second stage includes a second pull up device (323) and a second pull down device (322) having the latch node (311) therebetween, wherein at least one gate of the first pull up or first pull down device (302, 303) is directly coupled to a gate of the second pull up or second pull down device (322, 323). An output inverter (330) is coupled to the latch node (311).

Abstract: An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device(418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420).

Abstract: A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

Abstract: The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the “clock-to-Q period”) is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal.

Abstract: The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first nodes. The first charge/discharge path and the second charge/discharge path include: two first switching units, connected to the first nodes, and configured to control, according to an input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path; and a second switching unit, disposed between a second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge.

Abstract: A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermineddelay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal.

Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.

Abstract: A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurality of input signals are in predetermined logic levels; and a decoding unit for decoding output signals of the latch unit in order to control ODT operation.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: A state-holding circuit having improved stability at high temperatures includes a bi-stable circuit capable of assuming one of two reversible and stable states. The bi-stable circuit comprises a plurality of logic components (e.g., transistors) arranged into two sides. Because each of the logic components has a leakage current and/or resistance that varies significantly as a function of temperature, one or more stabilization components, such as transistors or other devices, may be connected to a side of the bi-stable circuit to balance the leakage currents and/or resistances of each side. In certain embodiments, the sole function of the stabilization components is to balance the leakage currents and/or resistances of each side.

Abstract: A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connected to the clock signal, and an output signal s2, an OR circuit having a first input connected to the data input, a second input connected to s2, and an output signal s3, and a FLIP-FLOP circuit whose first input is connected to s2, whose second input connected to s3, and whose output is OUT Q.

Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second feedback loop, where the first and second feedback loops each have a first node and a second node, where the first holding element is designed such that upon a first clock edge of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node in the first feedback loop, where the first node in the first feedback loop is coupled to the first node in the second feedback loop in order to transfer the signal value which is on the first node in the first feedback loop to the second holding element upon a second clock edge of the clock signal and to output the signal value on the noninverting output, wherein the second node in the first feedback lo

Abstract: Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output of the first logic gate, and has a gate terminal coupled to the first word line. The second pass gate is coupled between the bit line and a second storage node at the output of the second logic gate, and has a gate terminal coupled to the second word line. The bit line and one of the word lines can be used to selectively set or reset a given static memory cell, if desired, without affecting other memory cells along the word line. In some embodiments, the static memory cell is a configuration memory cell of a programmable logic device (PLD).

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.

Abstract: Methods and apparatus are provided for trapping metastability events to provide a metastable-free output signal. Values of an input signal compared to at least three different threshold voltages are latched at a predetermined point in time. A first intermediate signal is activate when all of the at least three corresponding latched values are in a first logic state. A second intermediate signal is activated when all of the at least three corresponding latched values are in second logic state. An output signal is placed in a first predetermined logic state in response to the second intermediate signal and is changed from the first predetermined logic state to a second predetermined logic state in response to the first intermediate signal.

Abstract: A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: A latch circuit is configured so that even if a power-on-reset circuit is not operated in putting a power supply to work, a depletion type MIS transistor is connected as a pull-down element to an output terminal of an RS latch to thereby reliably activate the RS latch in a reset state, whereby a circuit or a semiconductor integrated circuit device is prevented from being unintendedly operated. Furthermore, channel impurities of the depletion type MIS transistor are introduced into only a part, whereby it is possible to realize a semiconductor integrated circuit device which is excellent in safety and which is readily operated with less current consumption and with low cost.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A differential latch circuit with a differential reset function includes a first arrangement of transistors configured to perform a latch function and a second arrangement of transistors, connected to the first arrangement of transistors, configured to perform a reset function. The first arrangement of transistors includes branches having three cascoded transistors, and the second arrangement of transistors includes branches having two cascoded transistors. This configuration enables the latch circuit to use lower power supply voltages relative to conventional latch circuits that require four more cascoded transistors.

Abstract: Method and apparatus are provided for trapping metastability events to provide a metastable-free output signal. At least three successive values of an input signal are latched successively over a predetermined period which is less than half of a fundamental period of the input signal to provide at least three corresponding latched values. First and second intermediate signals are activated when outputs of all of the at least three corresponding latched values are in respective first and second logic states. An output signal is placed in a first predetermined logic state in response to the second intermediate signal and is changed from the first predetermined logic state to a second predetermined logic state in response to the first intermediate signal.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: For use in a strobed comparator circuit of the type comprising a decision circuit and a set-reset (SR) latch for holding an output of the decision circuit, an apparatus and method is disclosed for reducing output delay between two complementary output signals of the SR latch. During the reset phase of the SR latch, only one input to the SR latch changes state while the other input to the SR latch returns to its previous logic state. Information relating to the change of logic states of the decision circuit and of the SR latch is provided to two feed forward transistors that send the information directly to the SR latch output that is likely to have an output signal delay. The apparatus and method of the present invention causes the output signals of the SR latch to arrive at their respective output terminals at approximately the same time.

Abstract: A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit ties to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset drivers to exhibit like capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

Abstract: The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: A programmable logic circuit is provided that solves glitch problems associated with asynchronous logic operations associated with conventional look-up tables by utilizing a preset dominant transparent latch element to replace a conventional look-up table. Since latch elements are normally present in programmable logic circuits (e.g., FPGAs) no additional circuitry is necessary to implement the approach of the present invention. In one exemplary embodiment, an FPGA is provided which includes an array of programmable latch elements, and an array of programmable flip-flop elements generating flip-flop output signals. One or more of the latch elements are programmed to form a preset dominant transparent latch (PDTL) such that the data signals are coupled to the data inputs and preset inputs of the latch. In this manner, the latch operates to replace conventional look-up tables by operating as a primitive OR or NOR gate to generate a desired output.

Abstract: An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.