Abstract: Radio Frequency (RF) amplifiers with voltage limiting using non-linear feedback are presented herein. According to one aspect, an RF amplifier comprises an amplifier circuit having an input terminal and an output terminal and a non-linear feedback circuit having an input terminal and an output terminal. The input terminal of the non-linear feedback circuit is connected to the output terminal of the amplifier circuit and the output terminal of the non-linear feedback circuit is connected to the amplifier circuit to reduce the gain of the amplifier circuit when an RF voltage swing present at the input terminal of the non-linear feedback circuit exceeds a predefined threshold. In one embodiment, the output terminal of the non-linear feedback circuit is connected to the input terminal of the amplifier circuit. In another embodiment, the output terminal of the non-linear feedback circuit is connected to a bias circuit of the amplifier circuit.

Abstract: A liquid crystal display panel and a liquid crystal display apparatus are provided. The liquid crystal display panel includes a driving circuit, wherein the driving circuit includes a power module for inputting an initial voltage to a common electrode, and a feedback unit for adjusting the initial voltage of the power module based upon the actual voltage at the common electrode, so that the actual voltage at the common electrode is equal to a preset voltage.

Abstract: A device for use with an RF generating source, a first electrode, a second electrode and an element. The RF generating source is operable to provide an RF signal to the first electrode and thereby create a potential between the first electrode and the second electrode. The device comprises a connecting portion and a current sink. The connecting portion is operable to electrically connect to one of the first electrode, the second electrode and an element. The current sink is in electrical connection with the connection portion and a path to ground. The current sink comprises a voltage threshold. The current sink is operable to conduct current from the connecting portion to ground when a voltage on the electrically connected one of the first electrode, the second electrode and the element is greater than the voltage threshold.

Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Abstract: A differential RS latch circuit has a series structure wherein a first differential transistor pair, a second differential transistor pair and a third differential transistor pair are connected in three stages, and jointly function as one current switch. A first diode serving as a first level shift element is provided in a first current path between a power source node and a grounding node, and second and third diodes serving as second and third level shift elements are provided in a second current path between the power source node and the grounding node. The number of elements provided in the first current path is equal to that of elements provided in the second current path. As a result, the first and second current paths are equal to each other in response speed to a signal, and thus an hazard is prevented from occurring even at the time of the switching operation between the first and second current paths.

Abstract: A load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. The load stage also includes a switch connected between the first node and the second node. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

Abstract: An electric multiple-valued register for electrically maintaining a multiple-valued digital signal of a ternary value of (0, 1/2, 1), quaternary value of (0, 1/3, 2/3, 1) or quinternary value of (0, 1/4, 2/4, 3/4, 1) instead of a binary digital signal such that 1 digit is of 0 or 1 is realized by inserting an element having a stair shaped voltage-current characteristic into a coupling circuit of a conventional flip-flop circuit. It may be used for a quantization circuit with the aid of a step characteristic, a multivalued memory, a multivalued register, a multivalued loop memory, a multivalued pattern matching circuit, a voice recognition divide, pattern recognition device, or a associative memory device.