Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.

Abstract: The present invention relates to a pulse conditioning circuit including a first switch terminal having a first leg connected to a DC power source and a second leg. A second switch terminal is also provided having a first leg connected to an electrical ground and a second leg electrically connected to the second leg of the first switch. Pulses resulting from switch closures at the switch terminals are provided at the node where the second legs of both switch terminals are coupled. This node is preferably coupled to a low-pass filter, which is further coupled to a latch circuit providing a conditioned pulse output. The latch circuit is adapted to provide a first logic state output when the input of the latch is provided with a high logic state and a second logic state output when the input of the latch is provided with a low logic state. The high logic state input is provided when a switch connected to the first switch terminal is closed.