Abstract: A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

Abstract: Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.

Abstract: A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A logic circuit has a signal line for transmitting a digital signal as a voltage level and a loop circuit serving as a memory unit for storing the digital signal. Input and output terminals of the loop circuit are connected to the signal line. The loop circuit is a partial circuit having an even number (at least two) of signal inverters each having capacitive input load. At least one of the input and output terminals of the loop circuit is connected to an electric resistor. The loop circuit has a time constant T that is determined by the product RC of the resistance R of the resistor and the intentional and parasitic capacitance C of the signal inverters. The time constant T has a given relationship with the operation frequency of the logic circuit. The resistance R and capacitance C form a low-pass filter. The logic circuit provides different equivalent circuits in high and low frequency regions above and below the cutoff frequency of the low-pass filter.

Abstract: A differential RS latch circuit has a series structure wherein a first differential transistor pair, a second differential transistor pair and a third differential transistor pair are connected in three stages, and jointly function as one current switch. A first diode serving as a first level shift element is provided in a first current path between a power source node and a grounding node, and second and third diodes serving as second and third level shift elements are provided in a second current path between the power source node and the grounding node. The number of elements provided in the first current path is equal to that of elements provided in the second current path. As a result, the first and second current paths are equal to each other in response speed to a signal, and thus an hazard is prevented from occurring even at the time of the switching operation between the first and second current paths.

Abstract: A high speed bi-polar D latch circuit uses cross-coupled current-biased buffering transistors to block control current from output resistors so that the clock and data controls are not connected directly to the outputs of the latch. The memory cell portion of the latch which controls the latch output is constantly biased. Latch output swing is minimally affected by clock/data switching due to the buffering action of the emitter followers on the latch outputs. Changing the latch state is accomplished by changing the base-emitter voltage of the buffering transistors through the emitter followers. The circuit provides greater noise immunity at latch outputs during clock transitions and faster rise/fall times of output waveforms.