Abstract: Provided is a semiconductor integrated circuit which includes a logical operation circuit, a clock generator, a relay circuit, and a signal generating unit that are integrated. The clock generator generates multiphase clocks. The relay circuit distributes the generated multiphase clocks to the logical operation circuit. The signal generating unit detects phase states of the distributed multiphase clocks and, based on the detected phase states, generates an analog voltage signal having a voltage value indicative of a phase error in the multiphase clocks.

Abstract: A method of synchronization of a digital circuit includes selecting a first site and a second site from a plurality of different sites of the digital circuit where a signal to be synchronized occurs; passing a first signal, which is the signal to be synchronized of the first site, via a first line that starts at the first site, ends at the second site, and contacts each of the sites just once, to the second site; passing a second signal, which is the signal to be synchronized of the second site, via a second line that starts at the second site, ends at the first site, and contacts each of the sites just once, to the first site; determining, for each site, a first phase shift between the signal to be synchronized of this site and the first signal, and a second phase shift between the signal to be synchronized of this site and the second signal; and determining, from the first and second phase shifts of each site, a delay for each site, with which the signal to be synchronized of the respective site is delayed

Abstract: A phase detector is described, comprising a pair of output-latched half-transparent (OLHT) module each receiving two input terminals with an inverse connection relationship with respect to two input signals as compared to each other, wherein each OLHT module of the pair comprises two stages of logic operation unit connected in series and a latch circuit electrically connected to a latter one of the two stages of logic operation unit and latching and output an output signal.

Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.

Abstract: Disclosed is a PLL circuit including a phase frequency detector (PFD) for comparing phase and frequency between an input signal and an output signal, a charge pump circuit for charging a capacitor when an up-signal from the PFD is activated, discharging the capacitor when a down-signal is activated, and for outputting the terminal voltage of the capacitor as a control voltage, and a VCO for outputting an output signal of a frequency in accordance with the control voltage. An output of the VCO is fed back as an output signal to the PFD as input. The PFD includes a delay adjustment circuit for exercising control for resetting the up-signal and the down-signal with a preset delay as from a time point both up-signal and the down-signal have been activated. There is also provided a comparator amplifier circuit for comparing a reference voltage, corresponding to a control voltage when both up-signal and down-signal are activated, to supply first and second control signals to the delay adjustment circuit.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node.

Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.

Abstract: The present invention provides a phase comparison signal processing circuit which processes an output rectangular wave signal of a digital phase comparator of a PLL, expands a pullable-in frequency width of the PLL and shortens a synchronization time. The phase comparison signal processing circuit includes a first signal path which is parallel-connected between a voltage shifter for converting a rectangular wave signal to a bipolar signal and an output terminal and comprises a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and a common addition circuit, a second signal path comprising a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and the addition circuit, and a control signal generator for individually controlling the integration holding circuits and the gate circuits of the first and second signal paths.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A DLL with a reduced size, a semiconductor memory device including the DLL and a locking operation method of the DLL that includes a phase detector, a delay line, a delay controller, a delay circuit and an output buffer. The phase detector detects phase difference between input clock signals and feedback clock signals, and outputs phase detection signals according to results of the detection. The delay circuit delays reference clock signals during predetermined time and outputs the delayed signals as feedback clock signals. The output buffer outputs internal clock signals in response to delay clock signals. The reference clock signals are generated by one of circuits that exist in an actual output path of the internal clock signals. Accordingly, it is possible to reduce skew between the data strobe signals/the output data signals and the external clock signals, which may occur according to conditions in manufacturing processes, and to reduce the occupation area of the DLL.

Abstract: A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and a master phase detector and lock circuit for comparing relative phases of the master and slave timing and in response generating and applying delay adjust signals to the phase adjust circuit at a dynamically adjusted rate which is related to the relative phase in order to synchronise the slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of the slave and master timing.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied to a bias input, the method comprising the steps of selecting a first and second control vernier from the plurality of verniers; programming the first control vernier to a first delay; programming the second control vernier to a second delay; triggering the first and second control verniers together to generate respective first and second delay signals; generating a difference pulse signal having a duty cycle corresponding to a difference between the generated first delay signal and second delay signal; comparing the duty cycle of the pulse signal to a duty cycle of the reference pulse signal to generate a difference signal pulse, the difference signal being coupled to the bias input of the verniers to adjust the delay range such that the duty cycle

Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply.

Abstract: VDLs and delay an input clock and a return clock and provide a delayed input clock and a delayed return clock to a PLL part. The PLL part receives the delayed input clock and the delayed return clock, and outputs a PLL output so that these signals are synchronous with each other. This PLL output finally returns as a return clock via an external circuit. A PD detects a phase difference between the input clock and the return clock, and outputs a phase comparison signal. A control logic circuit determines a degree of phase advance of the return clock with respect to the input clock based on the phase comparison signal, and controls a delay time of the VDL so that a phase error between the input clock and the return clock is zero.

Abstract: A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

Abstract: A semiconductor integrated circuit include a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A multiphase comparator circuit includes a first differential stage; a first switching arrangement for connecting an output of the first differential stage to an input of a load circuit; and two or more regeneration stages. Each regeneration stage is connected to a load circuit and to the first switching arrangement. A clock-controlled second switching arrangement selectively provides an operating current to the regeneration stages. The first and second switching arrangements have switches that are driven so as to operate the regeneration stages in a manner temporally offset from each other.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input unit for receiving an external clock signal from which a clock input signal is created; a delay monitor for receiving a clock output signal to monitor a time delay introduced on the clock input signal; and a phase detection unit for receiving the clock input signal and an output of the delay monitor for determining a difference in phase between the clock input and output signals to produce a shift control signal. A shift register for controlling the adjustment of the time delay and a delay line for adjusting the time delay are also provided in the delay locked loop. Both the shift register and the delay line have a ring configuration on their outputs.

Abstract: A DLL circuit has edge detecting/phase comparing portion 2 that generates an original comparison signal that is set to logic “1” when the rise-up of feedback clock FBCLK is prior to the rise-up of reference clock RCLK, and also set to logic “0” when: the rise-up of the feedback clock FBCLK is subsequent to the rise-up of the reference clock RCLK, outputs the original comparison signal as subsequent phase comparison result CMPR when it is detected that the level of the reference clock RCLK and the level of the feedback clock FBCLK are varied in same directions within time T0, and keeps the output logical level of the phase comparison result CMPR and outputs it as subsequent phase comparison result CMPR when it is detected that the level of the reference clock RCLK and the feedback clock FBCLK are varied in opposite directions within the time T0.

Abstract: A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among the two or more output signals from the phase control unit, and generates one or more correction signals each having a value corresponding to a deviation of one of the detected phase differences from a desired phase difference. The phase detector feeds the one or more correction signals back to the phase control unit so as to make the detected phase differences equal to desired phase differences, respectively.

Abstract: A delay-locked loop (DLL) circuit having a master-slave structure wherein the DLL circuit includes a master delay loop and a slave stage. The master delay loop delays an external clock signal by a predetermined delay time and generates a feedback signal which is phase-synchronized with the external clock signal. The slave stage delays the external clock signal by the predetermined delay time and generates an internal clock signal. The master delay loop includes a phase comparator, a delay controller, a delay part and a compensation delay part. The slave stage includes a low-pass filter and a slave delay part. The master delay loop may have a structure in which a plurality of delay parts are connected in series. According to the DLL circuit, the high frequency phase noise of the internal clock signal can be minimized in a locked state.

Abstract: A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second inverters are configured of inverters of different sizes. A phase comparator compares a delay clock's phase with a reference clock's phase and a result of the phase comparison is referred to to count addresses which are in turn used to selectively drive the inverters configuring the first and second inverter circuits, to allow the fine delay circuit to output a signal having a phase between signals having therebetween a phase difference of a fixed amount. Thus the clock's phase can be adjusted with high precision.

Abstract: There is disclosed a 90-degree phase shifter so configured that an input signal is supplied through a variable gain amplifying circuit and a phase adjusting circuit to a low pass filter and also supplied through another variable gain amplifying circuit and another phase adjusting circuit to a high pass filter, so that the low pass filter and the high pass filter generate output signals, respectively, which have a 90-degree phase difference therebetween. An amplitude error and a phase error between the output signals are detected, so that the variable gain amplifying circuits are gain-controlled by the detected amplitude error, and the phase shift amounts of the phase adjusting circuits are controlled by the detected phase error. Thus, the amplitude error and the phase error attributable to the variation in the device characteristics and the parasite component can be removed, so that it is possible to obtain the output signals having the 90-degree phase difference with no amplitude error and no phase error.

Abstract: A skew adjusting circuit can carry out optimum correction of skew by automatically reading skew amounts of transmission paths with a receiving-side IC, without setting particular skew amounts externally. The skew adjusting circuit includes delay generating circuits, a plurality sets of flip-flops, decoders and selectors. Each delay generating circuit is provided to one of channels, and includes delay elements, each of which has a same delay amount. Each set of the flip-flops is provided to one of the delay generating circuits except for a first delay generating circuit corresponding to a reference channel signal. The flip-flops of each set receive an output of a final delay element of the first delay generating circuit as a clock signal, and receive tap outputs of the associated one of the delay generating circuits. Each decoder receives outputs of the flip-flops of one of the sets of flip-flops.

Abstract: A method and apparatus for generating an output clock signal having a frequency fO derived from a reference clock signal having a frequency fR, such that f 0 = M N ⁢ f R , is satisfied, wherein M and N are integers and M<N. In the method, a plurality of intermediate clock signals are provided having a frequency fX, such that f X = 1 X ⁢ f R , wherein X is an integer close in value to N/M, and having a predetermined phase relationship with respect to one another.

Abstract: This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A first feedback loop controls the phase difference between the in-phase and the quadrature outputs while a second feedback loop controls the amplitude difference between the in-phase and quadrature outputs. The phase splitter device controls the amplitude difference and the phase difference between the in-phase and the quadrature outputs by a common mode of control signals and a differential between the control signals, respectively. In this way, the phase splitter device generates in-phasing and quadrature outputs that have a phase difference and an amplitude difference that is substantially equal to the amplitude and phase set values (e.g., zero and 90°) using a single set of control signals.

Abstract: A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant current source electrically connected to an emitter of the third NPN transistor. The phase comparison circuit compensates for an offset current between a reference current and an output current, and as a result, can properly operate at a low voltage.

Abstract: A phase difference detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, including: a phase comparison unit for comparing the phase between the external synchronous signal and the internal synchronous signal to generate the phase difference detection signal; an equalization pulse detection unit for detecting an equalization pulse from the external and internal synchronous signals and generating a control signal for controlling the output of the phase difference detection signal from the phase comparison unit according to an equalization pulse detection signal; an output selection unit for masking the phase difference detection signal from the phase comparison unit in an equalization period and providing the phase difference detection signal in a non-equalization period according to the control signal form the equalization pulse detectio

Abstract: A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.

Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

Abstract: A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached.

Abstract: A phase correction circuit for correcting an antiphase component of a one-dimensional input signal is provided. The circuit contains a phase tracker, an antiphase detector, and an antiphase corrector. The phase tracker detects a decision error in the one-dimensional input signal having a phase error and outputs a phase-corrected signal in response to the decision error. The antiphase detector detects whether or not the phase-corrected signal is in antiphase and outputs a corresponding phase control signal. The antiphase corrector corrects a phase of the phase-corrected signal in accordance with the phase control signal. A method for performed by the phase correction circuit is also provided.

Abstract: A switched bridge circuit includes a low voltage to high voltage interface which selectively controls an input to a high side switch. A controller compares the voltage across the interface, the state of the high side switch, and the output of the circuit. If hard switching is detected by the controller, it latches the voltage across the interface thus keeping the high side switch on to allow the hard switching to occur. If soft switching is detected, the high side switch is kept off. A source follower is used to drive the high side switch so that the circuit output follows the interface output thereby avoiding oscillation. A falling edge detector for the output of the circuit uses the inherent parasitic capacitance of a high voltage device which also forms a bootstrap diode. When the output drops, the parasitic capacitance feeds a resistance which causes a driver to actuate. A second falling edge detector uses the inherent parasitic capacitance of the level shifter switch which is another high voltage device.

Abstract: A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.

Abstract: An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.

Abstract: There is provided an adjustment circuit which delays a first and a second signal by a desired delay. After the first and the second signal are inputted to the adjustment circuit via a first and a second signal line, respectively, the first and the second signal are exchanged and are inputted via the second and the first signal line, respectively. A detection circuit receives the first and the second signal from the adjustment circuit, and detects the phase differences of these signals, before and after the exchange. The holding circuit holds a first phase difference detected by the detection circuit before the exchange, and holds a second phase difference detected by the detection circuit after the exchange. When the holding circuit holds the first and the second phase difference, a comparison circuit compares these phase differences. A counter counts in accordance with the comparison results of the comparison circuit, and sets the desired delay of the adjustment circuit.