Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree.

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Abstract: A timing generating circuit formed as an LSI of CMOS.FETs is provided which enables correction of the variations of delay amount caused by the heat generated in the CMOS.FETs due to the propagation of pulses through the CMOS.FETs. A sub delay element 22 is connected in series to a main delay element 21 in which a timing is set and placed in the vicinity of the element 21. Both delay elements are connected in the same cell structure and arrangement. The sum of initial values of the delay amounts of respective delay elements is made to be a constant value. An input pulse to the main delay element is also supplied to a reference signal generator part 27 which outputs a reference signal using a reference clock after the lapse of the constant value from the time the input pulse is inputted. A time difference between this reference signal and the output from the sub delay element 22 is detected by a time difference detection part 29.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: Disclosed is a phase detection apparatus for accurately calculating the phase of an input digital complex baseband signal point independently of its amplitude value, without requiring any large-capacity arc-tangent table memory and within a practical calculation time. This phase detection apparatus rotates the phase of the input signal point in a clockwise direction and determines whether the rotated signal point agrees with a reference phase point. If the rotated signal point leads the reference phase point, the signal point is further rotated by an angle onehalf of the predetermined angle. If the rotated signal point lags behind the reference phase point, the signal point before the rotation is rotated by a half angle of the predetermined angle. Rotational angles, 180.degree., 90.degree., 45.degree., . . . , for the individual rotations are stored in a table.

Abstract: A phase-synchronizing type clock signal generating circuit including a DLL (delay line loop) circuit, capable of performing a similar operation for a DLL circuit even under the low-speed operation as in the high-speed operation. The clock signal generating circuit includes: a delay circuit for delaying an internal clock signal upon receipt of a reference clock signal externally provided; a selector circuit which selects and outputs either the reference clock signal or an output from the delay circuit, in accordance with a selector signal externally provided; a buffer circuit which delays the internal clock signal for as long as a signal passing delay time duration for the selector circuit; and a delay line loop which delays the reference clock signal upon receipt of an output signal from the selector circuit and that from the buffer circuit.

Abstract: A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.

Abstract: A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads.

Abstract: The correction circuit comprises a first quadrature phase comparator intended to receive as input two signals which are desired to be in quadrature and to have equal amplitudes. Phase adjustment means are firstly intended to correct the phase of at least one of the signal to re-establish a phase difference of 90.degree. therebetween. The correction circuit further comprises means to effectuate the sum and the difference of the signals which it receives as input and to supply the sum and the difference to a second quadrature phase comparator intended to supply as output a second error signal representative of the difference of the effective phase shift of these calculated signals and 90.degree.. The second error signal is finally supplied to amplitude adjustment means intended to correct the amplitude of at least one of said signals.

Abstract: A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.

Abstract: A digital phase detector that stores four sequential digital samples in a shift register. The contents of the shift register is evaluated at one half the clock frequency which generated the digital samples. The digital phase detectors predicts what the value should be for each of the two middle samples in the shift register. The predicted value and the actual value of each middle are used to generated a correction signal. The correction signals for the two middle samples are then added to produce a total correction signal which is to be used in controlling the phase and frequency of the voltage controlled oscillator in the phase locked loop generating the clock that controls the generation of the digital samples.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A digital phase shifter for phase-shifting a cyclic input signal includes first--third dividers 1, 4 and 8, first and second phase detectors 2 and 6, first and second voltage controlled oscillators (VCOs) 3 and 7, and a digital comparator 5. The input signal F(IN) and a clock signal F(VCO3) output from the first VCO3 are divided by N and M at the first and second dividers, respectively and phases of the divided signals are compared at the first phase detector 2, whereby the leading edges of the input and clock signals are synchronized. The second divider 4 also generates a count value (m) representing a cycle order number to the comparator, where it is compared with a preset value (.phi.) for determining the amount of phase shift, and an equate pulse EQ5 is generated when the compared values are the same.

Abstract: A local clock system uses a numerically controlled oscillator referenced to a stable oscillator to generate local clock signals under microprocessor control. Two feedback loops provide inputs to the microprocessor for maintaining synchronization with the external clock reference; a frequency locked and a phase-locked loop. The relatively wide-band frequency-locked loop is used to acquire initial synchronization with the external clock reference when the external clock is restored after having been lost or is switched to a new source. The phase-locked loop has a narrow bandwidth and provides a large attenuation of any jitter on the incoming reference with a resultant low output jitter. The microprocessor provides a hold-over operation upon loss of the external clock reference and when the external reference is restored it slowly adjusts the output clock frequency to match that of the reference, limiting the rate of adjustment so as not to exceed a specified allowable jitter in the local clock output.

Abstract: A sampling phase detector for a data bit synchronizer produces a constant level in the absence of data bit transitions. Reference voltages are provided and a switch selects between these reference voltages to provide an output which changes only when a data bit is detected and otherwise remains at a constant level. A loop filter operates together with the sampling phase detector to provide the constant voltage output in the absence of data bit transitions.

Abstract: An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.

Abstract: In methods and apparatus for controlling a phase relationship of two signals, a supplementary phase adjustment signal is generated. The supplementary phase adjustment signal has a zero value when an actual phase relationship of the two signals deviates from a desired phase relationship by less than a threshold phase deviation, and has a non-zero value when the actual phase relationship deviates from the desired phase relationship by more than the threshold phase deviation. The phase relationship of the two signals is adjusted in response to a sum of the supplementary phase adjustment signal and a phase adjustment signal which is proportional to the deviation of the actual phase relationship from the desired phase relationship. The methods and apparatus are particularly applicable to alignment of clock signals with data signals.