Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A comb signal generator that includes at least two signal sources that each provide a signal, wherein the signals provided by the at least two signal sources are shaped similarly. The com signal generator also has a combining circuit connected with the at least two signal sources, wherein the combining circuit is configured to combine the signals provided by the at least two signal sources, thereby generating a combined signal. Further, the com signal generator includes a clipping circuit connected with the combining circuit, wherein the clipping circuit is configured to receive and process the combined signal, thereby generating a comb signal. Further, a method of providing a phase and amplitude reference is described.

Abstract: An electronic circuit and method are provided. The electronic circuit includes an in-phase (I)-quadrature (Q) amplifier including an I cascode branch and a Q cascode branch, the IQ amplifier configured to receive a differential input and control signals, control, based on the control signals, gate voltages in the I cascode branch and gate voltages in the Q cascode branch, generate an I output signal with the I cascode branch, and generate a Q output signal with the Q cascode branch, and a quadrature coupler configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase shifted output.

Abstract: A measuring device with jitter compensation is provided. The measuring device including at least one analog-to-digital converter, a clock source, and at least one phase shifter. In this context, the at least one phase shifter is configured to receive a clock signal from the clock source and to adjust the respective phase.

Abstract: Active filters that may be utilized in various types of radio devices (e.g., receivers and/or transmitters) are disclosed. In some implementations, high dynamic range mixers implementing a polyphase multipath approach may be utilized in the active filters. Such mixers may satisfy the high dynamic range and image suppression requirements when they are configured for radio frequency applications.

Abstract: Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage.

Abstract: A variable effective size magnetic resonator includes an array of resonators each being one of at least two substantially different characteristic sizes and a mechanism for detuning at least one of the resonators from the resonant frequency of the variable effective size magnetic resonator.

Abstract: In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay stage has at least one inverter having a leg having a current regulator that controls current flowing through the leg and thereby controlling gain of the delay stage. The VCO receives three control signals that affect the amount of delay applied by each delay stage and therefore the VCO output frequency: a first applied to control the power-regulating circuitry, a second applied to at least one transistor gate in the current regulator, and a third applied to at least one transistor body in the current regulator. The power-regulating circuitry has a parallel configuration of a power-regulating transistor, a first capacitor, and a switched-capacitor leg having a second capacitor and a switch for controlling settling time. The capacitors regulate the power supply without a dedicated, opamp-based voltage regulator.

Abstract: Amplifier circuits and methods of cancelling the Miller effects in amplifiers are disclosed herein. An embodiment of an amplifier circuit includes an input and an output. An amplifier is connected between the input and the output of the circuit. A voltage source is connected to the output, wherein the voltage source output is one hundred eighty degrees out of phase with the voltage output by the amplifier, and wherein the voltage source cancels gain due to the Miller effect of a Miller capacitance between the input and output.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.

Abstract: An exemplary phase interpolator includes a first to a fourth differential pair. Each of the differential pairs includes a first and a second transistor and a stabilizing capacitor connected between a source coupled node and a reference voltage. The phase interpolator also includes a plurality of current sources and a group of switches to switch connections between the source coupled nodes of the differential pairs and the current sources so that (i) a first operating current is supplied to a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to a second selected one of the third and fourth differential pairs. Drains of the first transistors in the differential pairs are commonly connected and drains of the second transistors in the differential pairs are commonly connected to form a first and a second output node so that a differential output signal is output.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

Abstract: A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.

Abstract: The wideband programmable phase shifting circuitry includes a charge pump, a comparator, and a voltage reference generator block. An input signal controls the charge pump which charges and discharges a capacitor connected to an output of the charge pump. The comparator continuously compares the voltage across the capacitor with a reference voltage, ratio of VREF, which is generated by the voltage reference generator block. The voltage VREF is generated to compensate for power supply and integration process variations. The voltage reference generator is comprised of a charge pump unit, a frequency divider unit, switches, and two capacitors. The adjusted VREF ratio controls the comparator threshold level and hence a programmable phase difference between the input signal of the charge pump and the output signal of the comparator.

Abstract: A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

Abstract: An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

Abstract: A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.

Abstract: Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: The invention relates to a phase shifter which has at least two cascaded delay stages (1, 2), each including a first differential pair of bipolar transistors (Q1, Q1?) and a second differential pair of bipolar transistors (Q2, Q2?). The bases of the first differential pair (Q1, Q1?) serve as input nodes for the delay stage. The emitters of the first differential pair are coupled to a first current source (CS1), and their collectors are coupled to respective loads (D1, D1?; R1, R1?) to provide differential output nodes (OUT1, OUT1?) of the delay stage. The bases of the second differential pair (Q2, Q2?) are coupled to respective output nodes of the first differential pair (Q1, Q1?) of a delay stage, and their emitters are coupled to a variable current source (CS21, CS22, . . . ) for selectively adjusting the current (IA, IB, . . . ) through the second differential pair (Q2, Q2?). The input nodes of each following delay stage (2, . . .

Abstract: An interface system couples a fixed impedance device to a receiver for transmitting data signals at different data rates at different times. The interface system includes elements that are connected to provide different time constants of responsiveness to data signals of higher and lower data rates without distorting the data signals beyond usability.

Abstract: A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.

Abstract: An amplifier circuit comprising a transconductor device connected to a phase shifter section. The phase shifter section has an adjustable phase shift and an impedance at least partially dependent of the frequency of an input signal. In use, the adjustable phase shift is adjusted to have substantially the opposite value of a phase shift of the transconductor device. In an embodiment, the phase shifter section comprises a capacitor device and an adjustable resistor device which comprises an amplifier device with an input contact for receiving a resistance control signal; a first output contact connected to the capacitor devices and a second output contact connected to the transconductor device. The amplifier circuit further comprises a control device for providing said resistance control signal to the input contact of the amplifier device.

Abstract: An AMOLED display system, including an AMOLED display panel receiving a video signal, includes a video driver receiving the video signal and generating a video drive signal indicative of the video signal and referenced to a positive power supply voltage of the display panel, and a current driver coupled to an OLED pixel element receiving the video drive signal and the positive power supply voltage and providing a drive current to the OLED pixel element. The drive current is proportional to a current drive voltage which is indicative of the video signal and independent of the positive power supply voltage. In one embodiment, the video drive signal is indicative of the sum of or the difference between the positive power supply voltage and the video signal and the current drive voltage is indicative of the difference between the positive power supply voltage and the video drive signal.

Abstract: A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an output and a second portion of the first modulated input signal to an internal balancing node. The weighting system also is configured to steer a first portion of the second modulated input signal to the output and a second portion of the second modulated input signal to the balancing node. The first portion of the first and second modulated input signals are summed at the output to provide an interpolated output signal having a phase angle that is between the first and second phase angles.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock signal at a desired phase. The clock phase interpolator circuit includes selectable differential transistor pairs coupled to variable current sources. Different differential transistor pairs are driven by clock signals of different phases provided by the delay locked loop circuit. Two differential transistor pairs are selected, and currents provided to the selected differential transistor pairs are adjusted to provide an output clock of the desired phase.

Abstract: A differential delay cell includes a current source for establishing an operating current and a differentially coupled transistor pair having a common node, two input nodes, and two output nodes. The common node is coupled to the current source, and the two output nodes are coupled to an impedance load. The impedance load establishes a time delay between each of the input nodes and a corresponding one of the output nodes. Differential output signals are generated at said two output nodes in response to input signals coupled to said two input nodes. An amplitude control device is coupled between the two output nodes for controlling an amplitude of the differential output signals being generated.

Abstract: A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of which is coupled to said common output. The gates are coupled to respective ones of the plurality of clock phases and their complements. Tails couple the other terminals of said switching transistors to ground. Each tail made up of a plurality of transistors. A load coupling the common output to a voltage.

Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.

Abstract: Circuits and methods for providing an accurate phase shift between a generated output signal and an input signal are disclosed. The circuits and methods enable any amount of accurate phase shift to be set without requiring significant changes in circuitry with each phase shift. The phase shift is set by a voltage applied to a feedback amplifier connected to a low-pass filter and a timer circuit that resets a latch circuit.

Abstract: The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the analogous input signal (S1) and the output signal (S2) thereof is fed back to the inverting input thereof in a negative feedback. Moreover, a second amplifier (3) is provided, whereby the non-inverting input thereof is connected to ground, the inverting input thereof is connected to the output signal (S2) of the first amplifier (2) by means of a series resistor (R2) and the output signal (S3) thereof is fed back to the inverting input thereof in a negative feedback and by means of a negative feedback resistor (R1). The negative feedback resistor (R1) and the series resistor (R2) are provided with the same resistance value. The aim of the invention is to process higher maximum levels of the source signal and to suppress noises of the second amplifier.

Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.

Abstract: A phase interpolator which includes cross-coupled switches and is configured to receive a plurality of input clock phases and generate a new output clock phase based on the input clock phases which are selected by the cross-coupled switches. The cross-coupled switches are controlled by selection inputs. The phase interpolator may be configured to receive four clock phases, but preferably is configured to receive eight clock phases. Preferably, the phase interpolator includes eight cross-coupled switches, such as two sets of four cross-coupled switches. Preferably, each set of switches is controlled by a different selection input. Hence, a first selection input controls one set of four cross-coupled switches, and a second selection input controls the other set of four cross-coupled switches. Preferably, each pair of switches—wherein each pair includes a switch from each set—is configured to receive the same clock phase.

Abstract: A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices which receive the input clock phases and receive the selection inputs, and includes cross-coupled switches which are connected to the selector devices and receive input clock phases therefrom. The selector devices select which input clock phases to provide to the cross-coupled switches based upon the selection inputs. The cross-coupled switches generate the output clock phase based upon the input clock phases which are received from the selector devices.

Abstract: A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at least one of addition and subtraction on the two detection signals after level adjustment to generate a pair of output signals having a phase difference of 90 degrees or a single output signal having a phase difference of 90 degrees with respect to one of the detection signals, and a position measuring apparatus including an output level adjuster, a scaling signal generator, a detector, an A/D converter, and a memory in addition, wherein the position measuring apparatus cancels a phase error so that a signal having a phase difference of 90 degrees can be obtained.

Abstract: A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolater circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.

Abstract: The integrated circuit generates an output clock signal with a phase shift relative to a first clock signal. The currents IE=I1 and IL=I2 can be weighted differently by means of control signals. A different phase shift of the output clock signal results depending on the weighting.

Abstract: A filter includes an FET and a capacitor in a phase shift network wherein the FET operates as a variable resistor. An impedance multiplier is coupled to the FET for increasing the range of resistance of the FET.

Abstract: An RF amplifier system and method are presented herein for varying the phase of an RF signal made up of a first train of pulses exhibiting a fixed frequency and fixed duty pulse cycle and wherein each pulse is of a fixed amplitude and duration. An integrator converts each pulse cycle of the RF signal into a dual slope symmetrical ramp signal. A first level signal and a second level signal are provided and are equally spaced from a reference level. The dual slope ramp signal is compared with the first and second level signals. A first pulse signal is provided for a time duration corresponding with the time duration that the ramp signal exceeds the first level signal and a second pulse signal is provided for a time duration corresponding with the time duration that the second level signal exceeds the ramp signal. First and second pulse generators respectively receive the first and second pulse signals and provide first and second trigger pulses.

Abstract: An input circuit for use in a semiconductor integrated circuit decreases a phase lag between a clock signal and an input signal. The input circuit includes a first amplifier that receives an external clock signal at a first input and a reference voltage signal at a second input, and generates an amplified clock signal, and a second amplifier that receives an external input signal at a first input and the reference voltage at a second input, and generates an amplified input signal. A latch circuit is connected to the first and second amplifiers and receives the amplified clock signal at its clock input and the amplified input signal at its data input. The first and second amplifiers receive a high voltage supply signal from a common a high potential power supply and a low voltage supply signal from a common low potential power supply.