Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Abstract: A differential phase splitter circuit for producing opposite phase signals from an input AC signal is provided. A first and second transistor is provided. The source of these transistors are connected to a common first node. Further, these transistors act as a differential amplifier. The gate of the first transistor receives an input AC signal. The drain of the first transistor produces a first output AC signal. Similarly, the drain of the second transistor produces a second output AC signal that is 180 degrees out of phase with the first output AC signal. A source resistor is provided, connected in series to the common first node and ground. Lastly, an LCR feedback circuit is provided. This feedback circuit is connected between the drain of the first transistor and the gate of the second transistor. The LCR feedback circuit couples at least a fraction of the amplitude of the first output AC signal to the gate of the second transistor for amplitude balancing and phase balancing.

Abstract: A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.

Abstract: An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Abstract: An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to a frequency lower than that of the input signal and one tuned to a frequency higher than that of the input signal. The loaded outputs are recombined in a vector summing network to synthesize the required phase shifted output signal. This technique permits implementation on a monolithic integrated circuit (MIC) with high gain at high frequencies (e.g. 10 GHz). It also allows a large dynamic range of operation and a large (i.e., greater than 90 degrees) controllable phase shift. This is accomplished without the use of variable reactance elements or any other components external to the MIC.

Abstract: The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branches to a first supply potential; a first capacitor connected between the output branches; two second resistors connected in series between the biasing branches; a second capacitor connected in series between the two second resistors; means for applying an input signal in the form of a differential current across the second capacitor; and means for supplying, as an output signal, the sum of the current in one of the first resistors and of a predetermined fraction of a corresponding component of the differential current constituting the input signal.

Abstract: A high frequency, current mode, single-ended-to-differential signal converter with low input impedance constant to very high frequencies and a balanced output signal even for large signals. A wide range of input voltages may be accommodated and a d.c. offset correction added. A circuit for achieving a precise fifty percent duty cycle digital signal is disclosed. A circuit for ensuring a 90.degree. phase differential between two signals needed for quadrature multiplication is disclosed. Unusual precision in phase control of the quadrature signals needed for modulation and demodulation of wireless signals is obtained by the use of feedback circuits in both the duty cycle generator and phase shifter.

Abstract: A phase shifting circuit has an oscillation circuit. The oscillation circuit is provided with a charging and discharging capacitor at which the oscillation signal is generated. The oscillation signal has a constant level period and a saw tooth wave period. A valve of current flowing through the capacitor is changed in the middle of the saw tooth wave period by an input signal. An output of the phase shifting circuit is phase-shifted by 90.degree. with respect to the input signal.

Abstract: An apparatus and method for performing spatial nulling in antenna electronics that provides an integrated solution of signal attenuation and bi-phase modulation. One implementation is comprised of load resistors and field-effect-transistors in a gallium arsenide component configured in such fashion as to provide attenuation and bi-phase capability in response to coupled control signals.

Abstract: The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of signals is selected for controlling when the output signal transitions from a first logic state to a second logic state, and one of the plurality of signals is selected for controlling when the output signal transitions from a second logic state to a first logic state wherein the output signal has a pulse width being a function of the selection of the plurality of signals.