Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.

Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.

Abstract: A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.

Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Abstract: A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.

Abstract: The wideband programmable phase shifting circuitry includes a charge pump, a comparator, and a voltage reference generator block. An input signal controls the charge pump which charges and discharges a capacitor connected to an output of the charge pump. The comparator continuously compares the voltage across the capacitor with a reference voltage, ratio of VREF, which is generated by the voltage reference generator block. The voltage VREF is generated to compensate for power supply and integration process variations. The voltage reference generator is comprised of a charge pump unit, a frequency divider unit, switches, and two capacitors. The adjusted VREF ratio controls the comparator threshold level and hence a programmable phase difference between the input signal of the charge pump and the output signal of the comparator.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.

Abstract: Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.

Abstract: Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: The present invention is a system and method that facilitates measurement of timing variations (e.g., timing delays) in a semiconductor chip. The timing variations are measured and presented as digital values without extensive off chip measurement and analysis equipment. The timing variation measurements provides insight into timing variations (e.g., delays) inside a semiconductor chip and across different chips, including timing impacts experienced in end use after manufacturing. A timing variation measurement system includes a variation test signal generator for passing a signal through a portion of a circuit and generating a variation test signal. A variation test signal tracking component digitally counts cycles in a variation test signal and a control component controls the counting (e.g., the length of time the cycles are counted). Timing variation information, including a digital value associated with the variation test signal cycle count, can be communicated via pins and/or a processor interface.

Abstract: A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal.

Abstract: A method and apparatus is described that may be utilized to equalize modal velocity changes on a data bus. Modal velocity changes may be equalized by use of variable delays that may be used to equalize modal velocity changes.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.

Abstract: A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.

Abstract: An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates logical delaying/advancing data for a temperature change, and outputs the logical delaying/advancing data in every predetermined period. A temperature correction data input means receives the delaying/advancing data outputted by the temperature correction data creating means and outputs the logical delaying/advancing data to a logical delaying/advancing means. The logical delaying/advancing means operates a state of the frequency-dividing means in every predetermined period on the basis of the set logical delaying/advancing data to control the period of the frequency-divided output signal of the frequency-dividing means so as to be coincident with a desired period.

Abstract: The clock signal generator can be used to generate a first and/or a second output clock signal from an input clock signal. The rising and/or falling edges of the input clock signal are shifted using delay stages. The clock signal generator has a delay stage with a plurality of delay elements that are wired up in parallel and that have different delay lengths, and a selection device that is used to determine which of the output signals from the delay elements is to be output as the output signal of the delay stage.

Abstract: A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: In a control system a characteristic quantity of a process (1) exhibits a periodic disturbance. A measuring system (2) generates a measuring signal (Vm) which represents the characteristic quantity. A control device controls the process in response to the measuring signal (Vm). To reduce the periodic disturbance, the control device (3) comprises a delay circuit (4) which delays an input signal (Vin) related to the measuring signal (Vm) by a time interval (T) having the length of a period (Tp) of the periodic disturbance. The control device (3) comprises an analysis circuit (6) for deriving an analysis signal (Va) which is indicative of a deviation between the period of the periodic disturbance and the delay time. By means of a control circuit (13) and an adapter circuit (7), the delay time (T) is set in dependence on the analysis signal (Va) to a value for which the analysis signal (Va) indicates that the delay time (T) is equal to the period (Tp).

Abstract: A scan circuit includes a plurality of stages of cascaded pulse delay transfer circuits each including a single-phase-clock controlled inverter connected in cascade and configured to receive a given pulse signal from a preceding stage so as to transfer the received pulse signal to a next stage at a delayed timing in synchronism with a clock signal, and a two-input logic gate having a first input connected to an output of the associated single-phase-clock controlled inverter and a second input receiving the same clock signal. The two-input logic gate of an odd-numbered stage includes a NOR gate, which has an output connected to a non-inverting output buffer. The two-input logic gate of an even-numbered stage includes a NAND gate, which has an output connected to an inverting output buffer.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.

Abstract: An oscillator circuit including a current-controlled phase shift circuit and a feedback circuit including a quartz resonator is capable of varying the oscillation frequency in accordance with control current signals. A phase shift circuit included in the current-controlled phase shift circuit includes a first low-pass filter including a resistor and a capacitor, a first buffer amplifier, a second low-pass filter including a resistor and a capacitor, and a second buffer amplifier. The phase shift circuit has a significant gain at any frequency for oscillation. Especially an oscillation circuit implemented by an integrated circuit satisfies the suitable condition in which relative value of resistances and capacitances do not vary.

Abstract: A signal processing circuit delays a binary periodic input signal. Three series-connected delay devices produce output signals that are delayed in relation to the input signal. The delay of the delay devices can be controlled to a very high degree of accuracy, in that the delay devices include a plurality of mutually identical series-connected delay elements which are manufactured at one and the same time by common process steps in one and the same semiconductor process. A controller compares in a phase detector the phase of the input signal with the phase of the output signal from the last delay device, and on the basis thereof delivers control signals to the delay devices. These control signals control the delay devices in a manner such that an equal number of delay elements will be activated in each of the delay devices, such that the delay devices will have mutually the same delay.

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.

Abstract: A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.