Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Abstract: A method includes, in at least one aspect, selecting a first phase signal, where the first phase signal concurrently enables a first pair of switching elements; selecting a second phase signal, where the second phase signal concurrently enables a second pair of switching elements; and generating an interpolated phase signal by providing a connection between a switching element of the first pair of switching elements to an output node and providing a connection between a switching element of the second pair of switching elements to the output node.

Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Abstract: A method for providing an interpolated output signal includes, in at least one aspect, receiving a plurality of phase signals applying each phase signal of the plurality of phase signals to switching elements of a first set of switching elements receiving a plurality of select signals, applying an asserted select signal to a first switching element of a second set of switching elements to provide a connection between a first switching element of the first set of switching elements and a first output terminal, and applying the asserted select signal to a second switching element of the second set of switching elements to provide a connection between a second switching element of the first set of switching elements and a second output terminal.

Abstract: A phase interpolator is provided that, in one implementation, includes first and second interpolator modules, each having an output in communication with an output node. The first interpolator includes an input to receive a first plurality of input phase signals, and a selector to select one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes an input to receive a second plurality of input phase signals, and a selector to select one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the selected ones of the first plurality of input signals and each of the selected ones of the second plurality of input signals are included in an interpolated output signal.

Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: There is provided an oscillator for generating an oscillating signal having desired frequency, having a reference oscillating section for generating a reference signal having predetermined frequency, a plurality of first variable delay circuits, connected in cascade, for receiving the reference signal and outputting the received reference signal by sequentially delaying by almost equal values of delay, a phase comparing section for comparing phase of the reference signal generated by the reference oscillating section with phase of a delay signal outputted out of a final stage of the plurality of first variable delay circuits, a delay control section for controlling a value of delay of the plurality of first variable delay circuits so that the phase of the reference signal becomes almost equal to the phase of the delay signal outputted out of the final stage of the plurality of first variable delay circuits and a frequency adding circuit for generating the oscillating signal in which edges of the respective in

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: The invention relates to a method and related circuitry for multiple phase-splitting. The method includes: while generating M output clocks with a same frequency f1 and different phases, generating N reference clocks with a same frequency (M/N)*f1 and different phases (wherein M>N), and triggering (N/M) frequency division using different periods within each reference clock to generate (M/N) output clocks of different phases for each reference clock, such that the M output clocks of different phases are generated from the N reference clocks of different phases.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Abstract: An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Abstract: In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such as those in a ring oscillator or a delay line device receiving overall control of its output signals by a global control signal. The global control signal may be issued by a phase-locked loop, delay-locked loop, or other like structure. A second set of delay cells is provided to further delay the output signals produced by the first set of delay cells. The second set of delay cells are controlled by individual control signals uniquely calibrated in accordance with a preferred embodiment of the invention to provide uniform (or substantially) uniform time spacing between output signals.

Abstract: An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within corresponding memory devices, e.g., flip-flops when triggered by the phase shifted clock signals. These levels may be at a high level (e.g., the clock signal has the value “1”) or a low level (e.g., the clock signal has the value “0”). A “phase selection table” stores multiple entries, each of the entries includes multiple clock level values. Each of the entries specifies values used to determine when the phase shifted clock signals transition from the high level to the low level. This transition point signifies a 180 degree phase shift. Using this transition point, other phase shifts can be determined.

Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in a series between a high-level potential HL and an output terminal U1; an NMOS transister N1 and an NMOS transistor N1′ are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1′ through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1′ through an inverter IV2.

Abstract: In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal. At least one k-to-(n−k) weighted phase interpolator has a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of &thgr; to generate an output signal having a phase of (n−k)x+k&thgr;/n where k is 1, 2, . . . , n−1. At least one second delay circuit is connected to the k-to-(n−k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.

Abstract: An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and column address lines in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heater element is well suited for igniting a fuel cell such as a fuel cell in an array of fuel cells disposed in a thin film microthruster.

Abstract: A variable phase shifting circuit includes a resistance unit and a variable capacitance unit. The resistance unit includes at least one resistor element. The resistance unit input a first signal and a second signal and also output a third signal and a fourth signal. The variable capacitance unit includes two base-to-emitter capacitors of two transistors. The variable capacitance unit is connected to the third signal and the fourth signal. The two base-to-emitter capacitors is varied by controlling collector currents of the two transistors. The third signal and the fourth signal are produced by shifting phases of the first and second signals based on the at least one resistor element and the two base-to-emitter capacitors.

Abstract: (1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by different amounts. The bit phase adjusting circuit selects one of the data from this set and outputs it to a bit change detecting circuit having a second group of delay gates which are connected in series. (2) In the bit change detecting circuit, at a time controlled by a reference clock signal, it is judged whether or not the input and the output data of a pth-stage delay gate of the second delay gate group coincide with each other and whether or not the output data of the pth-stage delay gate and a (p+1)th-stage delay gate coincide with each other. A change point detecting signal is generated which shows whether or not a change point of the output data from the pth-stage delay gate is within a specified range before and after the judgement time.

Abstract: A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal.

Abstract: The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branches to a first supply potential; a first capacitor connected between the output branches; two second resistors connected in series between the biasing branches; a second capacitor connected in series between the two second resistors; means for applying an input signal in the form of a differential current across the second capacitor; and means for supplying, as an output signal, the sum of the current in one of the first resistors and of a predetermined fraction of a corresponding component of the differential current constituting the input signal.

Abstract: According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a phase lock loop, and receives a control voltage from the phase lock loop so as to generate a clock signal with a frequency according to the control voltage and to delay and output the clock signal. A second pulse generator generates two-phase clocks by using delayed signals generated by the second delay circuit. Switches are used for switching between a system clock output terminal during an actually active time and a system clock output terminal during testing.

Abstract: In a ring oscillator, a delay unit includes an input stage having a first and a second input port and a first and a second differential output port. At least two delay units are coupled together so as to form the ring oscillator. The delay unit further includes a first capacitor coupled to the first differential output port of each one of the delay units and a second capacitor is coupled to the second differential output port of the delay unit. A switching accelerator is coupled to the first and second capacitors so as to reduce the time it takes to switch between charged and discharged states for the capacitors.

Abstract: A first basic clock supplied from outside is delayed by a first delay circuit to generate a second basic clock which is fed to a frequency divider to generate a group of multi-phase clocks, each of which has a clock width equal to an integer number multiple of the clock width of the second basic clock and has a phase delay sequentially by a value equal to an integer number multiple of the clock period of the second basic clock, wherein the (n-1)th multi-phase clock and a nth multi-phase clock neighboring to each other in the phase sequence, and the first basic clock, are fed to a delay generating circuit as inputs, which comprises a second delay circuit for delaying the (n-1)th clock in the phase sequence, and a circuit arrangement for generating an output clock phase having a delay time relative to the nth clock, being equal to an smaller value of one half clock width of the first basic clock minus a delay time of the first delay circuit and a delay time of the second delay circuit.

Abstract: A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator.