Abstract: A integrated circuit includes a clock generator and a multiplexing latch circuit. The clock generator generates first and second latching clock signals in response to a select signal and a clock signal having a clock signal waveform, each of the first latching clock signal and the second latching clock signal having the clock signal waveform. The multiplexing latch circuit selects either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal, and stores and outputs the selected data.

Abstract: Certain aspects are generally directed to an apparatus for wireless communication, implemented using a configurable phase shifter network. The configurable phase shifter network generally includes a first switch coupled to a common terminal of the phase shifter network, a first phase shifter coupled between a first terminal of the phase shifter network and the first switch, a second switch coupled in parallel with the first phase shifter, a third switch coupled to the common terminal, a fourth switch coupled to the first terminal, and a second phase shifter coupled between the fourth switch and the third switch.

Abstract: A quantum communication system for distributing a key between first and second units, the system being configured to implement phase-based measurement device independent quantum cryptography, the system comprising first and second units adapted to apply phase shifts to light pulses and a detection unit adapted to cause interference between light pulses received from the first and second units and measure said interference, wherein the first and second units each comprise at least one phase modulator adapted to apply a phase shift, said phase shift comprising a global phase component and a relative phase component, wherein said global phase component represents a phase shift selected randomly in the range from 0° to 360° from a fixed phase reference and said relative phase component is a phase shift selected randomly from 0°, 90°, 180° and 270° from the phase shift introduced by the global phase component.

Abstract: A phase shifter is provided. The phase shifter includes a first phase shifter that is continuously adjustable within a range of 0 degrees to 90 degrees, two 4-way switches each configured to selectively switch on one of a capacitance, an inductance, an open circuit, and a short circuit under control of a control voltage, and a bridge. A first input end and a first output end of said bridge are respectively connected to a first 4-way switch of the two 4-way switches. A second input end of said bridge is connected to an output end of said first phase shifter or a second output end of said bridge is connected to an input end of said first phase shifter.

Abstract: A phase shifter is provided. The phase shifter includes a first phase shifter that is continuously adjustable within a range of 0 degrees to 90 degrees, two 4-way switches each configured to selectively switch on one of a capacitance, an inductance, an open circuit, and a short circuit under control of a control voltage, and a bridge. A first input end and a first output end of said bridge are respectively connected to a first 4-way switch of the two 4-way switches. A second input end of said bridge is connected to an output end of said first phase shifter or a second output end of said bridge is connected to an input end of said first phase shifter.

Abstract: Provided is a phase shifter having a high phase difference in a microwave band. The phase shifter includes a first phase shifting unit configured to receive an input signal having a predetermined frequency, receive a first control signal and a second control signal operating contrary to the first control signal, output the input signal as it is when the first control signal is activated, and output the input signal to have a lead phase as much as a predetermined phase, and a second phase shifting unit configured to receive a second signal outputted from the first phase shifting unit, receive the first control signal and the second control signal, output the second signal to have a lagged phase as much as a predetermined phase when the first control signal is activated, and output the second signal as it is when the second control signal is activated.

Abstract: Provided is a differential signal transmission apparatus that transmits a differential signal expressed by a potential difference between a positive signal and a negative signal, including a positive signal transmission line that transmits the positive signal; a negative signal transmission line that transmits the negative signal; and a delay compensating circuit that compensates for a time difference between the positive signal and the negative signal with a variable compensation time.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: Disclosed is an integrated circuit device in which a 90-degree phase shifter is implemented. The 90-degree phase shifter includes four input capacitors all having equal capacitance and four output capacitors all having equal capacitance. The input capacitors and the output capacitors are alternately arranged in a loop-shape array in plan view. Eight resistors of the 90-degree phase shifter are arranged inside the annular shape in which the capacitors are arranged.

Abstract: A radio frequency amplifier including a long tail pair of transistors provided with a tail current source. The bases of the transistors are driven by emitter follower transistor provided with collector load resistors. Feedback capacitors ensure stability and feedback resistors bias the amplifier without degrading noise performance. The amplifier may be driven unbalanced while retaining good second harmonic distortion performance.

Abstract: An apparatus comprising a first calibration circuit and a phase shift network stage. The first calibration circuit may be configured to generate a control signal. The phase shift network stage may comprise one or more tunable phase shift elements and be configured to provide a tunable impedance. The phase shift network stage may be tuned in response to the control signal and a conductance of the tunable phase shift elements.

Abstract: There is disclosed a phase shifter using a polyphase filter, which achieves a broad band, suppresses errors in both amplitude and phase, and achieves low power consumption. A driving section includes a voltage-to-current conversion circuit for converting a voltage value of an input signal Si into a current value, and outputting an input current signal Ci. An RC polyphase filter 2 outputs a corresponding polyphase phase-shifted current signal Co according to supplying of the input current signal Ci. A load circuit 3 includes a polyphase current-to-voltage conversion circuit for converting a current value of the polyphase phase-shifted current signal Co into a voltage value, and outputting an output signal Vo.

Abstract: Structures and methods for CMOS voltage controlled phase shift oscillators are provided. The CMOS voltage controlled phase shift oscillators, or phase shift circuit, includes any odd number of stages coupled in series. Each stage includes a CMOS amplifier. A phase shift network is coupled to the CMOS amplifier. The CMOS amplifier provides a gain and allows a small phase shift in each stage to eventually provide a signal which is 180 degrees out of phase with the input signal. In the CMOS amplifier, the PMOS transistor is a diode connected PMOS transistor which acts as a low valued load resistance. In the phase shift network, an NMOS transistor is used as a voltage variable resistor for providing a resistance value in the circuit.

Abstract: In order to provide a more flexible adjustment of signal delay times in a circuit configuration containing a line device and a number of electronic components accessing it, it is proposed to add additional capacitances, which can be varied in a controllable manner. In addition, the capacitances are to formed in a region of the existing components.

Abstract: A phase delay arrangement for connecting high speed digital ICs, wherein a substantial majority of delay is provided via added passive delay elements. The phase synchronization delay arrangement (circuit connection, system and method) adds delay to the signal propagation path between a driving circuit 110 and receiving circuit 130, in order to match signal propagation between a transmitting/receiving circuit pair. Such phase synchronization delay arrangement is provided substantially by added passive components or devices, e.g., added signal line length, inductors, capacitors, which provide a majority or mainstay of the delay, but can further include single ones of flow-through latches, drivers, and programmable delay lines.

Abstract: A skew adjusting circuit can carry out optimum correction of skew by automatically reading skew amounts of transmission paths with a receiving-side IC, without setting particular skew amounts externally. The skew adjusting circuit includes delay generating circuits, a plurality sets of flip-flops, decoders and selectors. Each delay generating circuit is provided to one of channels, and includes delay elements, each of which has a same delay amount. Each set of the flip-flops is provided to one of the delay generating circuits except for a first delay generating circuit corresponding to a reference channel signal. The flip-flops of each set receive an output of a final delay element of the first delay generating circuit as a clock signal, and receive tap outputs of the associated one of the delay generating circuits. Each decoder receives outputs of the flip-flops of one of the sets of flip-flops.

Abstract: A differential amplifier includes a first amplifier transistor whose base terminal is coupled to an emitter terminal of a first emitter-follower transistor, a second amplifier transistor whose base terminal is coupled to an emitter terminal of a second emitter-follower transistor, a first emitter impedance across which the emitter terminals of the first and second amplifier transistors are coupled to each other, while base terminals of the emitter-follower transistors can be supplied with a differential voltage for controlling the differential amplifier.

Abstract: A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (3) is started to generate an integration value (ios). At a certain instant (t1), the analog integration operation is interrupted to start counting (2) clock pulses (Clk). A selected number (N;N2) of clock pulses (Clk) is counted to obtain a sub-period (T2). The analog integration operation is resumed at the end of the sub-period (T2) at the integration value (ios) reached at the start of the sub-period (T2). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Abstract: The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity or simultaneous dual polarity/dual beam signals by placed-array modules. Additionally, an improved phase shifter design that is smaller said requiring fewer electronic components than prior art phase shifters is disclosed. In particular, the phase shifter requires only a single control line for each stage of the phase shifter.

Abstract: Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and second inverter chains, each having a plurality of series-connected inverters. A first signal, which may be a digital logic signal, is applied to an input of the first inverter chain. A second signal, which may be a clock signal used to latch the logic signal in an integrated circuit, is applied to an input of the second inverter chain. The inverter chains may be constructed such that the inverters of the second chain have a stronger drive capability than the corresponding inverters of the first chain. Capacitive coupling is provided between outputs of inverters of the first chain and outputs of corresponding inverters of the second chain.

Abstract: The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branches to a first supply potential; a first capacitor connected between the output branches; two second resistors connected in series between the biasing branches; a second capacitor connected in series between the two second resistors; means for applying an input signal in the form of a differential current across the second capacitor; and means for supplying, as an output signal, the sum of the current in one of the first resistors and of a predetermined fraction of a corresponding component of the differential current constituting the input signal.

Abstract: An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to a frequency lower than that of the input signal and one tuned to a frequency higher than that of the input signal. The loaded outputs are recombined in a vector summing network to synthesize the required phase shifted output signal. This technique permits implementation on a monolithic integrated circuit (MIC) with high gain at high frequencies (e.g. 10 GHz). It also allows a large dynamic range of operation and a large (i.e., greater than 90 degrees) controllable phase shift. This is accomplished without the use of variable reactance elements or any other components external to the MIC.

Abstract: Phase shift amplifier formed by a differential pair of input transistors each collector of which transistors is connected to a respective phase shift resistor and to a phase shift capacitor, whereas the other ends of each phase shift resistor form nodes A and B respectively, while the other ends of the phase shift capacitors are connected in a cross-coupling. According to the invention, the nodes A and B are connected to the input of amplifiers of the transimpedance type at the output of which amplifiers a differential signal is available which is phase shifted relative to the differential input signal.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

Abstract: An oscillator circuit including a current-controlled phase shift circuit and a feedback circuit including a quartz resonator is capable of varying the oscillation frequency in accordance with control current signals. A phase shift circuit included in the current-controlled phase shift circuit includes a first low-pass filter including a resistor and a capacitor, a first buffer amplifier, a second low-pass filter including a resistor and a capacitor, and a second buffer amplifier. The phase shift circuit has a significant gain at any frequency for oscillation. Especially an oscillation circuit implemented by an integrated circuit satisfies the suitable condition in which relative value of resistances and capacitances do not vary.

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.