Abstract: A system for generating in-phase and quadrature phase signals is provided. The system includes a first and a second differential output, such as from a sinusoidal oscillator. A first injection-locked frequency divider, such as one that uses an LC oscillator in conjunction with cross-coupled transistors, receives the first differential output and generates a in-phase or in-phase output. A second injection-locked frequency divider receives the second differential output and generates a quadrature phase output.

Abstract: An active quadrature signal generator produces poly-phase quadrature signals necessary in high frequency transmit and receive elements of a communication system. The quadrature signals are produced using the phase difference between a load representing a low-pass filter characteristic and a load representing a high-pass filter characteristic and the quadrature signal is then used in the differential structure to produce amplified signal having 4 quadrature phases. The device can reduce a loss characteristic of the signal and additional power consumption for compensating for it in a common poly-phase quadrature filter having only conventional resistors and capacitor.

Abstract: When two sine-wave signals in quadrature, the integral of the output is equal to zero. Conversely, when an in-phase signal is inputted as one multiplicand and the output is set to zero, a quadrature signal is derived from the second multiplicand automatically. Any analog multiplier can be used. Examples using differential pair and conductance multiplier have been demonstrated. The multiplier operates over a wideband, and the in phase and quadrature signals can be equalized automatically.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT−) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.

Abstract: The present invention is directed to a phase shifting arrangement for generating a set of mutually orthogonal signals. In one aspect, the invention provides a system that includes a phase shifting unit for receiving an input signal. The phase shifting unit includes a first phase shift circuit for generating a first output signal phase-shifted by a first amount with respect to the input signal, a second phase shift circuit for generating a second output signal phase-shifted by a second amount with respect to the input signal, and a third phase shift circuit for generating a third output signal phase-shifted by a third amount with respect to the input signal.

Abstract: A bi-directional vector rotator that can be used to provide outputs having phases that are rotated in clockwise and counter clockwise directions relative to that of the input signal. The bi-directional vector rotator includes a product term generator that receives a complex input and a complex carrier signal and generates product terms. Combiners then selectively combine the product terms to generate the outputs. By sharing the same product term generator for both clockwise and counter clockwise phase rotations, the bi-directional vector rotator can be implemented using less circuitry than that for a conventional design employing two uni-directional vector rotators. Moreover, only one complex carrier signal is needed by the bi-directional vector rotator instead of two for the conventional design. Further simplification in the design of the bi-directional vector rotator can be achieved by selecting the proper sampling rate for the complex input.

Abstract: A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a second output clock signal that is phase shifted a positive 90° with respect to the first output clock signal. The operation of the circuit may be responsive only to the input clock signal. In other words, the circuit may not require a reset signal to operate in a deterministic fashion.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: A circuit configuration for generating an output signal orthogonal to an input signal includes a delay device having an input to which an input signal is applied, an output at which an output signal is available, and a control input for controlling a time lag. A multiplier device has inputs being coupled to the input and the output of the delay device and has an output. A device for low-pass filtering is connected between the output of the multiplier device and the control input of the delay device.

Abstract: An electronic device which includes a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of the periodic signal. The multiplier circuit is formed on the basis of an EXCLUSIVE-OR gate (20), which receives the periodic signal, and a frequency divider circuit (22) connected between the output and an input of the gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which makes it feasible to perform a modulation of the type known as “zero demodulation”. The multiplier circuit can operate in accordance with CML technology (Current Mode Logic).

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: A frequency multiplier circuit comprises: a source oscillator configured to generate a source oscillator signal using a crystal oscillator; and n frequency multiplier circuits (n is an integer which is 2 or more), each of which includes a 90° phase shifter circuit configured to shift the phase of an input signal by 90°, and a mixer configured to generate a doubled signal of the input signal on the basis of the input signal and an output signal of the 90° phase shifter circuit, wherein the n frequency multiplier circuits are cascade-connected, the source oscillation signal being inputted to a first stage frequency multiplier circuit of the n frequency multiplier circuits, and a final stage frequency multiplier circuit of the n frequency multiplier circuits outputting a signal having a frequency 2n times as high as the frequency of the source oscillation signal.

Abstract: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.

Abstract: A DC-offset canceller in a receiver of a communication system using a burst signal including a training sequence with a predetermined periodicity at the head thereof is disclosed. In the canceller, a quadrature demodulator 112 converts the received burst signal to a base band signal. An AD converter 113 converts an output signal of the quadrature demodulator to a digital signal. A one-cycle delay element 114 makes a delay of an output signal of the AD converter 113 corresponding to one-cycle of the training sequence. A DC-offset detector 115 detects a DC-offset component in the converted signal by the AD converter 113 on the basis of an output signal of the AD converter 113 and an output signal of the one-cycle delay element 114. A subtractor 116 removes the DC-offset component detected by the DC-offset detector 115 from the output signal of the AD converter 113.

Abstract: A quadrature signal generation system which has a pair of input terminals for receiving a first A.C. signal and a second A.C. signal. The first A.C. signal and the second A.C. signal have a predetermined frequency and a phase relation of approximate 90° with each other. The system also has a multiplier circuit for providing a product of the first A.C. signal and the second A.C. signal, resulting in a third A.C. signal. Furthermore, the system has a square-difference circuit for providing a difference of a square of the first A.C. signal and a square of the second A.C. signal, the difference being a fourth A.C. signal. The frequency of the third A.C. signal, and the fourth A.C. signal are equal to twice the frequency of the first A.C. signal and the second A.C. signal, and the third A.C. signal and the fourth A.C. signal have a fine phase relation of 90° with each other.

Abstract: A delay locked loop circuit prevents occurrence of jitter and has a small chip area when it is realized as a semiconductor integrated circuit. The delay locked loop circuit includes a phase shifter, a compensation delay unit, a component coefficient extractor, a phase inverter, first and second component signal generators, and a phase mixer. In this structure, the delay locked loop circuit generates an output clock signal, the phase of which leads that of an externally-applied input clock signal by a predetermined delay time to compensate for a delay time which inevitably occurs in semiconductor integrated circuits. The phase shifter generates a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal. The compensation delay unit outputs a third clock signal, the phase of which lags that of the input clock signal by a predetermined delay time.

Abstract: This electronic device comprises a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of these periodic signals. This multiplier circuit (14) is formed on the basis of an <<EXCLUSIVE-OR>> gate (20), which receives said periodic signals, and a frequency divider circuit (22) connected between the output and an input of said gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which permits to perform a modulation of the type known by the name of “zero demodulation”.

Abstract: This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A first feedback loop controls the phase difference between the in-phase and the quadrature outputs while a second feedback loop controls the amplitude difference between the in-phase and quadrature outputs. The phase splitter device controls the amplitude difference and the phase difference between the in-phase and the quadrature outputs by a common mode of control signals and a differential between the control signals, respectively. In this way, the phase splitter device generates in-phasing and quadrature outputs that have a phase difference and an amplitude difference that is substantially equal to the amplitude and phase set values (e.g., zero and 90°) using a single set of control signals.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

Abstract: A transmitter having an integratable quadrature oscillator network for simultaneously producing a sine wave and a cosine wave. The digital direction of rotation (whether the frequency is positive or negative) input is slow rate limited (R, C3) and fed into a low gm transconductor (MOS1, MOS2) to softly switch between two pairs of transconductor amplifiers (TR1, TR2 and TR3, TR4) which together with two capacitors (C1, C2) form quadrature oscillators of opposite direction of rotation. By softly switching the quadrature oscillators out-of-band emissions are minimized in a subsequent mixing with a carrier signal to generate a frequency modulated signal.

Abstract: The invention produces an accurate quadrature relationship for a range of frequencies using passive components in the primary quadrature splitting circuits. A reference oscillator (202) generates a reference signal which is fed to a conventional passive quadrature splitter circuit (204). However, since the reference circuit provides signals over a range of frequencies, the output signals of the passive quadrature splitter may not have an accurate quadrature relationship. The output signals of the passive quadrature splitter are then equalized in magnitude, and the sum and difference of the signals are produced, which will be in an accurate quadrature relationship.

Abstract: Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained.

Abstract: A quadrature generator (100) includes a phase detector (125) having a set of differential inputs for coupling in-phase and quadrature signals (114,116) and a set of differential outputs for providing a phase error signal (135). Switches (122,127) are associated with the set of input terminals and with the set of output terminals. The switches (122,127) are synchronously controlled to switch around the signals at the input terminals and at the output terminals in concert, and in rapid succession. The operation of the switches (122,127) eliminates or reduces the effects of imperfections within the parallel paths of the phase detector circuitry (125), in order to produce a more accurate phase deviation signal.

Abstract: A clock signal generator includes a phase shifter for generating four clock signals having phases consecutively shifted from one another by 90 degrees based on an external clock signal, a mixer for mixing two of the four clock signals to output an internal clock signal, and an initializing circuit for selecting consecutively one and another of the four clock signals as an internal clock signal in an initializing period. A phase comparator compares the internal clock signal against the external clock signal in the initializing period to determine which of the internal clock signal and the external clock signal leads. The initializing circuit reduces the time length for locking of the internal clock signal to the external clock signal in an operational period of the mixer.

Abstract: An improved clock generation circuit is provided for changing the phase of one signal relative to the phase of another signal. Both signals presented to the clock generation circuit transition at the same frequency. One or both of those signals are delayed by dissimilar amounts to skew the phase difference between the signal pairs and 90.degree.. A phase detector, or logic gate, determines a phase differential between the incoming signals. A charge pump and storage device maintain a voltage level commensurate with that difference. The stored voltage is then used to control a feedback loop coupled from the output of the detector to a current path which traverses a buffer coupled between an input signal and a phase compensated output signal. The current path receives current necessary to change both the rise and fall rates produced by the buffer. According to another embodiment, two feedback loops may be used for a corresponding pair of buffers.

Abstract: In phase modulation of the quadrature signals of a multi-valued digital signal, when the signal state transition is .pi. [rad], the spectrum of a nonlinear amplifier extends beyond the transmission bandwidth, and the conversion distortion becomes conspicuous. A phase modulation apparatus includes a phase shifter (11) which receives a multi-valued digital signal, converts the digital signal into two quadrature signals such that a period for which the self phase shift amount of the digital signal on an orthogonal coordinate system becomes .pi./2 [rad] at the time of state transition of the digital signal is always obtained, and outputs the quadrature signals, a bandwidth limiting filter (12) which band-limits the outputs from the phase shifter (11), and a phase modulator (13) for phase-modulating the output from the bandwidth limiting filter (12). Since the state transition is .pi.

Abstract: The invention is directed to the realization of a .pi./2 phase shifter that provides accurate operation and moreover enables a reduction in current consumption. Such a .pi./2 phase shifter is constructed from a 1/2-frequency divider employing a T flip-flop and includes: a current source circuit which supplies to the T flip-flop a circuit current that determines the output frequency of the T flip-flop and which varies circuit current value according to control signals; and a frequency comparator that compares the output frequency of the T flip-flop and the local signal input frequency, and, based on the comparison results, varies the control signals in a direction such that the output frequency of the T flip-flop matches the local signal input frequency.

Abstract: The invention relates to a circuit arrangement for generating two signals having a phase difference of approximately 90 degrees. The invention is preferably applied in the demodulator of a radio receiver. In order to shift the phase of a signal one idea of the invention is to use a distributed resistance/capacitance circuit or a distributed RC circuit (Z.sub.10, Z.sub.20) in connection with a signal amplifying means (A.sub.1, A.sub.2). The operation of the circuit is not frequency dependent and a circuit adjustment is not necessarily required in order to calibrate the phase difference, because the distributed RC circuit can provide an substantially constant phase shift of .+-.45 degrees over a wide frequency range. The whole circuit can be integrated into one component, because a distributed RC circuit is easily made on the same integrated circuit substrate as the amplifying means, and thus the circuits can be made into a small size and at low manufacturing costs.

Abstract: An active phase splitter comprises two or more phase shift circuits. Each phase shift circuit comprises a number of active devices and capacitors. For a single-pole active phase splitter, within each phase shift circuit, two active devices are configured as a cascode amplifier. The first active device is configured as a common source amplifier and the second active device is configured as a common gate amplifier. A capacitor is connected across the gate and drain of the first active device to generates the necessary pole-zero pair for the phase shift circuit. The cascode configuration results in the desired transfer function and provides transconversion of voltage input to current outputs. Active phase splitters with two or more poles can be built using the same inventive concept.

Abstract: A discrete phase shifter and a method for discrete phase shifting in which an input signal is split into two signals. One of the split signals is phase shifted by a first fixed amount by a first fixed phase shifter cell, and the other split signal is phase shifted by a second fixed amount by a second fixed phase shifter cell. A selector is utilized to select at least one of the two split phase shifted signals and to input these to a vector summer. The vector summer synthesizes an output signal that is phase shifted with respect to the input signal. In this manner, the output signal is discretely phase shifted either by the first fixed amount, the second fixed amount, or, by selecting both of the split signals prior to vector summing, the sum of these amounts.

Abstract: An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.

Abstract: A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.

Abstract: A 90.degree.-phase shifter which operates in condition both of high-speed and low dissipation power, and an output signal with precise 90.degree.-phase difference is capable of taking off is provided. It causes input signals with complementary relation each other to input toward input terminals. A 1/2 frequency divider is composed of bi-differential transistors Tr5 to Tr12, and load resistances R1 to R4. The 1/2 frequency divider outputs a 90.degree.-phase difference signal to output terminals 11 to 14 based on collector current of signal input transistors Tr1 and Tr2. The collector current corresponds to the input signal. A duty ratio monitoring load 2 converts these collector currents into voltage. A low-pass filter 3 takes off a DC component corresponding to an offset from 50%-duty ratio of an input voltage from the converted voltage. A DC component amplifier amplifies the DC component thus performing feedback to the input terminals 8 and 9.

Abstract: A PWM controlling circuit includes a signal generator and two PWM controllers. The signal generator comprises an oscillator, a plurality of inverters, and two RC delay networks. The oscillator and the inverters are composed of elementary elements, respectively, such as diodes, resistors, inverters and capacitors. The PWM controlling circuit in accordance with the present invention can be implemented with low cost, and the duty cycles thereof are not limited to 50%.

Abstract: A digital and analog modulator is configured in a simplified circuit structure. The modulator includes a first frequency mixer circuit for modulating a carrier with an analog signal or a sine wave component of a digital signal, a second frequency mixer circuit for modulating a signal attained by shifting a phase of the carrier with an analog signal or a cosine wave component of the digital signal, and an adder for adding signals from the first and second frequency mixer circuits to each other.

Abstract: A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

Abstract: A phased array sector scanning ultrasonic system includes a separate beamformer channel for each respective element in an ultrasonic transducer array. Each beamformer channel has a three-stage complex FIR filter downstream of an analog-to-digital converter. Each filter circuit stage has a register pipeline, an in-phase FIR filter and a quadrature FIR filter. The first stage only has real samples, so there is a single pipeline. The other stages have complex inputs composed of in-phase (real) and quadrature (imaginary) samples, requiring a pipeline for each. Each register pipeline is made up of a multiplicity of registers connected in series. The number of registers in a given pipeline must equal the number of taps being used on the FIR filter immediately downstream of the register pipeline. The registers are clocked in synchronism and store successive echo data samples. Each register in the pipeline has an output connected to a respective tap of the corresponding FIR filter.

Abstract: A method for correcting an amplitude error between an I signal and a Q signal which are outputted from a quadrature detector including a first multiplier for multiplying a reference signal and a measured signal, a first integrator for smoothing the output of the first multiplier to generate the I signal, a 90-degree phase shifter for generating an auxiliary reference signal from the reference signal, a second multiplier for multiplying the auxiliary reference signal and the measured signal, and a second integrator for smoothing the output of the second multiplier to generate the Q signal. The method includes the step of inputting the auxiliary reference signal, instead of the reference signal, to the first multiplier to obtain a first output signal and inputting the reference signal, instead of the auxiliary reference signal, to the second integrator to obtain a second output signal.

Abstract: A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.

Abstract: The present invention provides a phase shifting apparatus and method. The phase shifting apparatus comprises a signal generator and a converting device. An input signal is converted by the offset signals from the signal generator, thereby producing an output signal with the same frequency as that of the input signal. The phase of the output signal is determined by the difference of the offset signals applied to the converting device. In particular, when two offset signals are in quadrature, the output signal becomes in quadrature with the input signal. When the two offset signals have the same phase, the output signal has the same phase as that of the input signal. Preferably, the converting device includes two cascaded offset means, each having a multiplier and a filter coupling to the multiplier. A plurality of converting means may be coupled in parallel to the signal generator.

Abstract: A circuit that provides samples of in-phase and quadrature components of an input waveform includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.

Abstract: Disclosed is an integrated circuit comprising a balanced set of inputs and a phase splitting circuit. The phase splitting circuit has a first input terminal that is coupled to the balanced set of inputs and a second input terminal that is coupled to the balanced set of inputs. The phase splitting circuit further comprises a balanced phase shifting network, a first set of output terminals, and a second set of output terminals. The balanced phase shifting network is coupled to the first: input terminal and the second input terminal. The first set of output terminals provides a voltage representative of a first voltage across a resistive portion of the balanced phase shifting network in response to an input voltage at the balanced set of inputs. The second set of output terminals provides a voltage representative of a second voltage across a reactive portion of the balanced phase shifting network in response to the input voltage at the balanced set of inputs.

Abstract: A digital phase shifter produces from an input clock signal quadrature pairs of the input clock signal. The quadrature pairs are mixed and summed in response to a desired phase angle control signal to produce a phase shifted clock signal. The quadrature pairs are produced from a counter having as input a signal at four times the input clock signal frequency, with one output being a signal at the input clock signal frequency. The clock output signal is delayed one-quarter of a cycle to form a quadrature clock output signal, and the in-phase and quadrature clock output signals are converted to complementary quadrature signals. The complementary quadrature signals are input to a double 4:1 multiplexer so as to produce for any selection signal a quadrature pair of signals at the output defining one of four quadrants.

Abstract: A double-balanced mixer circuit which consumes less power, and is capable of operating on a low voltage power source, because an output of a first signal having a phase lag of 90.degree. from a first frequency signal and an output of a second signal having a phase lead of 90.degree. over the first frequency signal are provided by means of a first phase shifter, an output of a third signal having a phase lag of 90.degree. from a second frequency signal and an output of fourth signal having a phase lead of 90.degree. over the second frequency signal are provided by means of a second phase shifter, thereby generating a radio frequency signal by mixing the first signal and the third signal in a first dual gate circuit, and generating a radio frequency signal by mixing the second signal and the fourth signal in a second dual gate circuit.

Abstract: A phase shifting circuit has an oscillation circuit. The oscillation circuit is provided with a charging and discharging capacitor at which the oscillation signal is generated. The oscillation signal has a constant level period and a saw tooth wave period. A valve of current flowing through the capacitor is changed in the middle of the saw tooth wave period by an input signal. An output of the phase shifting circuit is phase-shifted by 90.degree. with respect to the input signal.

Abstract: In this invention, in arranging a balance type input terminal group or output terminal group in an integrated circuit, the formation is provided with one terminal for grounding and two signal terminals adjacent to this grounding terminal on both sides. In connecting the output terminal group of the first integrated circuit and the input terminal group of the second integrated circuit with each other in such formation, the grounding terminals themselves and signal terminals themselves are respectively connected in one to one. Further, in the integrated circuit formed as mentioned above, among the bonding wires connecting the balance type input terminal group or output terminal group with an electrode group of an inner chip, the two bonding wires connecting the chip with the signal terminals are wired symmetrically with the bonding wire connecting the chip with the grounding terminal as a center.

Abstract: A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.