Abstract: A clock generation circuit includes: a preliminary clock generation circuit suitable for generating a first preliminary clock signal with a half of a target cycle, and generating a second preliminary clock signal by inverting the first preliminary clock signal; a clock doubler circuit suitable for generating first and second intermediate clock signals by respectively doubling the cycles of the first and second preliminary clock signals; and an edge trigger circuit suitable for triggering the first and second intermediate clock signals to output first and second output clock signals with the target cycle, respectively, according to the first and second preliminary clock signals.

Abstract: A scan driver includes scan signal outputting circuits, at least one of the scan signal outputting circuits includes a driving circuit and a buffer circuit. The driving circuit includes driving transistors. The driving circuit provides first and second driving signals to first and second driving nodes, respectively by turning on or off the driving transistors in response to clock signals and a scan input signal. The buffer circuit includes buffer transistors. The buffer circuit outputs a scan signal at an output node by turning on or off the buffer transistors in response to the first and second driving signals. The at least one of the scan signal outputting circuits performs a back-biasing voltage applying operation on at least one of the driving transistors and the buffer transistors when the driving transistors and the buffer transistors are turned on or off.

Abstract: A payment reader includes a tuning circuit that provides a tuned transmission source signal to an antenna for transmission. A sense circuit coupled to the antenna provides a measured transmitted signal to a binary phase detection circuit. The binary phase detection circuit filters and processes the signal to provide an analog phase signal that corresponds to a phase difference between the measured transmitted signal and the transmission source signal. A comparison circuit compares the analog phase signal to a reference signal, and a decision circuit adjusts the operation of the transmission circuitry based on the comparison.

Abstract: Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.

Abstract: A device comprises a first time generator for generating an internal time signal, a unit for receiving an external time signal at discrete synchronization times and a generator unit for producing a generated time signal, which generator unit is designed to calculate on the basis of an algorithm the generated time signal at a determination time between two synchronization times from a value of the external time signal at a previous synchronization time and from a value of the internal time signal at the determination time. Said algorithm includes an assumption of a proportionality between an advance in the internal time signal and an advance in the external time signal.

Abstract: A bipolar output charge pump circuit having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN), two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/?3VV, +/?VV/5 or +/?VV/6.

Abstract: A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator.

Abstract: A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.

Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.

Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.

Abstract: A system and method for reducing power consumption within clock distribution on a semiconductor chip. A 4-phase clock generator within a clock distribution network provides 4 non-overlapping clock signals dependent upon a received input clock. A reduced voltage swing clock generator receives the non-overlapping clock signals and charges and discharges a second set of clock lines in a manner sequenced by the non-overlapping clock signals. The sequencing prevents a voltage range from reaching a magnitude equal to a power supply voltage for each of the second set of clock lines. In one embodiment, the magnitude reaches half of the power supply voltage. The reduced voltage swing latch receives the second set of clock lines. The reduced voltage swing latch updates and maintains logical state based at least upon the received second set of clock lines.

Abstract: A novel high-speed phase splitter circuit (100) and method of operation are disclosed. This high-speed phase splitter (100) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (100) uses a phase splitting input stage (110, 130) followed by several amplification stages (150, 170) that are symmetrical and balanced in nature.

Abstract: A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal.

Abstract: A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.

Abstract: A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.

Abstract: A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.

Abstract: The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

Abstract: A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: According to some embodiments, non-overlapping clocks are to be generated.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

Abstract: A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input coupled to an overlap_en signal, a second input coupled to an inverted overlap_en signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal. Each clock inverter leg can further include an asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit and an input coupled to a waitr_signal that can be used to delay and adjust breadth of non-overlap. Each leg can further include a tri-state inverter circuit having a first input coupled to an output of the AVD circuit, and a second input coupled to the inverted first clock input signal.

Abstract: A phase splitter circuit including a clock delay section, a signal converter section and a signal generator section. The clock delay section uses a clock signal to produce first and second delayed clock signals that are time delayed versions of the clock signal. The second delayed clock signal is delayed more than the first. The signal converter section converts a static logic signal to a dynamic logic signal dependent upon the clock signal and the first delayed clock signal. The signal generator section produces a pair of complementary dynamic logic output signals dependent upon the dynamic logic signal and the first and second delayed clock signals. One of the output signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal. A method for generating a pair of complementary dynamic logic signals from a static logic signal.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A semiconductor integrated circuit includes a clock signal source for generating two-phase clock signals having spacing periods, a two-phase clock wiring for transmitting the two-phase clock signals to a plurality of internal circuits constructing the integrated circuit, and a waveform correction circuit having a plurality of MOS transistors of the same conductivity type connected between the two-phase clock wiring and a preset potential node and constructed to attain spacing periods of the two-phase clock signals. The waveform correction circuit corrects the blunted portions of the two-phase clock signals to stably attain spacing periods, and when it is distributed and arranged in portions far apart from the clock signal source, a problem of racing and the like can be effectively suppressed.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

Abstract: A non-overlapping clock generator that has its dead time adjustable without a complete re-design and re-fabrication. Certain terminals of certain devices of the non-overlapping clock generator are connected only by metal layers. This allows the circuit of the non-overlapping clock generator to be changed, adjusting the dead time, by changing only the masks used to fabricate the metal layers. This allows non-overlapping clock generators on wafers that have been partially fabricated to have their dead times altered from the original design.

Abstract: A non-overlapping clock generator that has its dead time adjustable without a complete re-design and re-fabrication. Certain terminals of certain devices of the non-overlapping clock generator are connected only by metal layers. This allows the circuit of the non-overlapping clock generator to be changed, adjusting the dead time, by changing only the masks used to fabricate the metal layers. This allows non-overlapping clock generators on wafers that have been partially fabricated to have their dead times altered from the original design.

Abstract: An integrated circuit device for synchronization of data in a data path includes a driver and a storage element coupled to the driver for driving the storage element. The storage element is coupled to the data path outside the data path. The integrated circuit employs a method of operation including passing a time pulse, sampling data during the time pulse, passing the data to a computation logic along a data path, and storing the sampled data in a storage element connected to but outside the data path.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.