Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

Abstract: An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.

Abstract: An ultrasound method and apparatus can include: transducer elements arranged in a sub-array for generating analog signals based on a return signal detected by the transducer elements during a receive interval; analog delay lines including individual delays unique to each of the transducer elements and calculated based on a linear delay slope for delaying the analog signals; an analog to digital converter for converting the analog signals to a digital signal; a digital beamformer with a digital delay based on one portion of the linear delay slope for delaying the digital signal; and a profile control register containing depth bits corresponding to multiple points for updating the linear delay slope during the receive interval to adjust for the multiple points within an image line.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: A display apparatus includes a first clock line providing a first clock signal and a second clock line providing a second clock signal. The first clock line includes a first main clock line and a first dummy clock line extending from the first main clock line, the second clock line includes a second main clock line and a second dummy clock line extending from the second main clock line, and the first dummy clock line and the second dummy clock line have different areas from each other.

Abstract: A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.

Abstract: The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.

Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.

Abstract: Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable reduced-frequency clock signals to the I/O cells of the chip. In this way, the reduced-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.

Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.

Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.

Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.

Abstract: A circuit is configured to generate periodic control signals including at least two mutually phase-shifted control signals. The circuit includes a plurality of generator circuits, where a separate generator circuit is provided for each control signal output by the circuit. Each generator circuit includes a phase value memory configured to store a phase value, where the phase value defines a phase shift. Each generator circuit includes an activation input and, in response to application of an activation level to the activation input, is configured to initiate a generation of a control signal which is phase-shifted by an amount defined by the phase value. The activation inputs of the generator circuits are connected together to an activation circuit for outputting an activation level to the generator circuits simultaneously.

Abstract: A phase shift generation circuit has an edge detector, which outputs a first and a second edge signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has first and second recycling timers, which output a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The circuit also comprises at least one flip flop which generates a phase shifted output pulse.

Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion, of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Abstract: There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2?n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.

Abstract: A differential SR flip-flop 100 receives a set signal S and a reset signal R, and generates a differential output pair Q and #Q. A first flip-flop FF1 generates a non-inverted output signal Q1 and an inverted output signal #Q1. A second flip-flop FF2 generates a non-inverted output signal Q2 and an inverted output signal #Q2. An averaging circuit 10 averages one output signal (Q1) of the first flip-flop FF1 and one output signal (Q2) of the second flip-flop FF2 so as to generate a first output signal Q3, and averages the other output signal (#Q1) of the first flip-flop FF1 and the other output signal (#Q2) of the second flip-flop FF2 so as to generate a second output signal #Q3. As a differential output pair, the differential SR flip-flop 100 outputs a signal that corresponds to the first output signal Q3 and a signal that corresponds to the second output signal #Q3.

Abstract: A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.

Abstract: Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution.

Abstract: A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: A phase interpolation circuit includes a waveform shaping unit and a phase interpolator. The waveform shaping unit adaptively waveform-shapes first or second phase offset input clock signal pair that is applied, to output first and second buffered clock signals having a rising time and falling time each of more than about a quarter of a period of the first and second offset input clock signals. The phase interpolator is applied to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.

Abstract: A data communication network may include two or more master clocks, and a synchronization system connected to the master clocks. The synchronization system may determine a time-base for the master clocks. The synchronization system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously.

Abstract: Embodiments related to configurable differential lines are disclosed herein.

Abstract: An apparatus for generating a plurality of signals is provided. The apparatus provided includes a first signal generation unit, including an input receiving a reference signal, and a plurality of outputs providing a first plurality of output signals being generated based on the reference signal, wherein any two of the output signals have a different phase. The apparatus provided further includes a second signal generation unit, including at least two inputs receiving at least two signals selected from the first plurality of output signals generated by the first signal generation unit, and a plurality of outputs providing a second plurality of output signals generated by interpolating the respective phases of the received at least two signals selected from the first plurality of output signals.

Abstract: A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract: The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay.

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change-of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches.

Abstract: Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

Abstract: A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.

Abstract: A frequency dividing phase shift circuit includes a first frequency divider and a second frequency divider. The first frequency divider is configured to perform 1/(2n+1) (n is a natural number) frequency division on an input signal having a frequency of (freq*2(2n+1)) (“freq” indicates a frequency) to generate a first signal having a frequency of (freq*2). The second frequency divider is configured to perform ½ frequency division on the first signal to generate 4-phase signals which are different in phase by 90 degrees one after another.

Abstract: Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: The invention relates to an electronic module (10) having organic components. The electronic module has a clock generator (2) having n organic switching elements (21) which are connected in series and are each constructed from organic components. The output of the nth organic switching element of the clock generator (2) is connected to the input of the first organic switching element of the clock generator (2).

Abstract: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A signal generator and method for generating a plurality of signals of differing phase. The signal generator comprises a first single-phase frequency divider locked with a 90° phase shift that includes a first output port providing a first output signal and a first internal node providing a first internal signal, a second single-phase frequency divider locked with a 90° phase shift that includes a second output port providing a second output signal and a second internal node providing a second internal signal, and a first feedback circuit. The first feedback circuit coupled between either: first and second output ports or first and second internal nodes. The first feedback circuit configured to phase-lock first and second output signals 180° apart when the first feedback circuit is coupled between first and second outputs ports and phase-lock first and second internal signals 180° apart when the first feedback circuit is coupled between first and second internal nodes.