Abstract: A fifty percent duty cycle detector includes a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine configured to receive the digital word and output the logical control signal and a ternary decision.

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A method for utilizing heat includes steps: converting heat to electrical power, and converting the electrical power to a PWM voltage signal to power a function module. Obtaining an input voltage of the function module and comparing the input voltage with a reference voltage. Increasing a duty cycle of the PWM voltage signal when comparing the input voltage is grater than the reference voltage. And decreasing a duty cycle of the PWM voltage signal when comparing the input voltage is less than the reference voltage.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A circuit for detecting fault conditions in a supply circuit includes a monitoring circuit and a comparator circuit. The monitoring circuit is operable to output a detection signal related to a control signal for the switched mode power supply. The control signal may be configured to operate at least one switch of the supply circuit between alternating activated and deactivated states to supply power to a load. The comparator circuit is operable to compare the detection signal to a range defined by first and second thresholds and output a fault signal according to a relationship of the detection signal to the range over a time period. Related methods of operation are also discussed.

Abstract: A voltage scaling circuit includes a first critical path and an edge detection unit. The first critical path includes an input and an output. The edge detection unit includes a first input, a second input, a counter and a time-to-digital converter (TDC). The input of the first critical path is electrically connected to the first input of the edge detection unit, and the output of the critical path is electrically connected to the second input of the edge detection unit. The counter is configured to measure a duration between an active edge of a start signal on the first input of the edge detection unit and an active edge of a stop signal on the second input of the edge detection unit in a clock period basis. The TDC is configured to measure a beginning portion and an end portion of the duration.

Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: The present invention discloses an electric signal outputting apparatus in a serial electric transmission system. The electric signal outputting apparatus includes a switching part for switchably generating high and low output signals in accordance with signal data and transmitting the output signals to a transmission path, an impedance matching part for matching an output impedance to the impedance of the transmission path, and an auxiliary switching part for subsidiarily supplying current to an output node in the transmission path and subsidiarily absorbing current from the output node in the transmission path when the switching part switches the generation between high and low output signals, wherein the auxiliary switching part conducts the supplying and the absorbing for a period shorter than a pulse width of a reference clock of the serial electric transmission system.

Abstract: A system for controlling the delay applied to one branch of a pulse width modulation amplifier. The delay typically incorporated whether input signal level is low and diminished when the input signal level increases. The system may be implemented using a switch, a level detector and a timer, which in conjunction determine whether the delay unit is included in the branch or bypassed. The system may also use a programmable delay that can adjust the period of delay applied or be programmed to operate as a pass-through where delay is no longer beneficial for providing high signal quality.

Abstract: A method for determining a time interval between leading edges of two adjacent cyclic input pulses of a series of cyclic input pulses. A sample of the cyclic input pulses is taken at each of a series of sampling times to produce sampling hits, each sampling hit being an indication of a presence of a cyclic input pulse, recording a count number at each of the sampling hits, determining initial sampling hits from the detected sampling hits, determining a minimum sampling interval between initial sampling hits, and determining a count number located at a back end of the minimum sampling interval, count numbers of the minimum sampling interval being used to determine a time interval between lead edges of two adjacent cyclic input pulses.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: A frequency sensor includes at least one a resistor element and a capacitor. A frequency is detected according to a charging/discharging time to/from the capacitor, thereby realizing a frequency sensor with reduced power consumption and reduced circuit scale. Further, plural resistors and plural capacitors can be provided, along with switches connected to the respective resistors and capacitors. Additionally, a time constant can be adjusted after production, whereby variations in production can be reduced. Furthermore, a self-diagnosis circuit can be included for determining whether the frequency sensor itself operates normally or not. Thus, a highly-reliable frequency sensor can be realized.

Abstract: A PWM controller that effectively transitions between normal mode and green power mode is disclosed. A driver provides a normal drive signal during normal operation. A pulse width detector detects the pulse width of the PWM signal and if the pulse width drops below a threshold the normal mode drive signal will be turned off and a pulse ON time measurer will begin storing the pulse ON time. When the total ON time reaches a total ON time threshold or the output voltage drops below a voltage limit, a green mode drive signal will be output to the power converter. During green mode the driver will continue sending the green mode drive signal at intervals until a heavy load condition when the green mode drive signal will be shut off and the driver will resume sending the normal mode drive signal.

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

Abstract: A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

Abstract: A digital modulator for driving a digital amplifier. The digital modulator has a subtractor which receives a digital input signal. A filter amplifier receives the output of the filter amplifier and is tuned to an idle frequency of the digital modulator. The digital modulator includes a delay element and a digital comparator. The digital comparator receives the output from the filter and applies it to the delay element. A feedback loop couples the output of the delay element to the subtractor.

Abstract: A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.

Abstract: A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.

Abstract: A space-efficient broadband balun (20). The balun (20) includes a first mechanism (44, 80, 82, 94, 96) for receiving an input signal (52, 54) having an undesirable component. A second mechanism (50) rejects the undesirable component via a waveguide transition (50). In a specific embodiment, the undesirable component is a common mode component. The first mechanism (44) includes an input microstrip waveguide (44). The waveguide transition (50) is a single microstrip-to-slotline transition (50) from the input microstrip waveguide (44) and to a slotline (32) in a ground plane (34, 36) of the microstrip waveguide (44). The slotline (32) is terminated at a first end (38) via a wedge (40) in the ground plane (34, 46). A second end (42) of the slotline (32) provides an output of the balun (20). The input signal (52, 54) includes a first input signal (52) and a second input signal (54), which are input at opposite ends (38, 42) of the input microstrip waveguide (44).

Abstract: A digital phase/frequency detector capable of being implemented with on-chip components and configured to detect signals having small modulation indices. Transition points within the signal are detected and the width between successive transition points measured and averaged. The average width measurements may be converted to width deviation values by subtracting out the width due to the carrier frequency. An interpolation may be performed between the current and previous values of the width deviation values to reduce quantization error. The interpolated values may be converted to frequency deviation values, and a predetermined number of the frequency deviation values may be averaged. The average frequency deviation values may then be equalized in order to reduce intersymbol interference. The resulting equalized values form soft estimates of the underlying source bits. Hard estimates of the source bits may then be derived from the soft estimates.

Abstract: Fault detection circuitry is provided for a PWM driver responsive to a PWM input signal to produce a PWM output signal, and includes a first circuit producing a scaled switching signal as a scaled representation of the PWM input signal. A second circuit is configured to produce a combined switching signal as a combination of the PWM output signal and the scaled switching signal, and a third circuit is configured to convert the combined switching signal to an analog output signal indicative of one or more fault conditions associated with the PWM driver. A number of comparators may be included with each responsive to the analog output signal and to a different one of a corresponding number of different references voltages, to produce a fault signal indicative of a particular one of the one or more fault conditions.

Abstract: A pulse detector has a leading edge detector and a trailing edge detector. A timing circuit is provided for determining the pulse duration between the leading edge and the trailing edge of a signal pulse; and a divider divides the pulse duration to produce a first timing pulse representative of a mid-point or peak of the signal pulse. An inventer may also be provided to produce a second timing pulse representative of troughs between signal pulses. A combiner may optionally be provided for combining the first and second timing pulses. The detector has application in signal cleaning circuits.

Abstract: An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the input logic signal. The filter may include a capacitor operably coupled to a controlled impedance, an inverter and a driver transistor, wherein the capacitor senses an edge of the input logic signal and, in combination with the controlled impedance, produces the pulse signal. The soft latch module is operably coupled to receive the pulse signal and to latch a logic value in accordance with the pulse signal.

Abstract: An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.

Abstract: When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.

Abstract: The lock detector circuit determines and indicates whether the PLL is in an in-lock mode or in an out-of-lock mode without using an external capacitor for controlling phase error. Moreover, the lock detector circuit indicates the operating mode of the PLL on a period-by-period basis relative to the period of the reference and feedback signals. Thus, the lock detector circuit provides real-time indication of the operating mode of the PLL.

Abstract: A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32&pgr; radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2&pgr; radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected.

Abstract: The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M) for storing the signal level which is applied to the input of the basic element, and the output of a storage element (M) is connected to the input of a next basic element. Furthermore, the circuit has a second input for supplying a second signal (S2) which is connected to a control input of each basic element. Given a first level of the second signal, the storage elements (M) take up the signal level stored in the preceding storage element, and given a second level of the second signal, the storage elements (M) retain the signal level respectively stored in them. Furthermore, the circuit has comparator units (XOR) to which, in each case, the signal levels stored by the storage units (M) of two adjacent basic elements are supplied.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: In a method for decoding digital PWM signal and a bus system, a peripheral unit, and a device therefor, the digital signal is decoded by integrating the pulse width of each bit and then comparing the integration result with a reference signal. The bus system includes dual wires, a device, and at least one peripheral unit. In an embodiment of the present invention, the bus system issued as an air bag system where diagnostic and deployment commands are sent via the bus wires to one or more peripheral units which control individual air bags.

Abstract: An output signal pulse width error correction circuit and method wherein errors in a data signal conforming to a communications protocol having a prescribed duty cycle are corrected by monitoring a duty cycle of the data signal, comparing the duty cycle to a duty cycle reference voltage corresponding to the prescribed duty cycle, and adjusting a pulse width of the data signal to conform to the prescribed duty cycle of the protocol. An embodiment is shown that low pass filters the input data signal to introduce greater slope to the input data signal which is then compared to a pulse width control voltage in order to generate an output data signal. The pulse width control voltage is produced by integrating the output data signal to obtain an average value corresponding to the duty cycle of the output data signal and comparing the average value to a duty cycle reference voltage corresponding to the prescribed duty cycle for the communications protocol.

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract: A semiconductor device which enables quick and reliable adjustment of the address transition detection pulse width has an address transition detector (ATD) and n PMOS transistors connected in parallel to an output terminal, the PMOS transistors behaving as pull-up transistors for the ATD. The PMOS transistors are controlled by controlling outputs of n controllers which generate the outputs from a pulse-like waveform applied to an input terminal thereof, thus the size of the PMOS transistors are substantially changed.

Abstract: An input signal variation detection circuit effectively detects transitions of input signals from a memory apparatus. The circuit includes a plurality of unit blocks for detecting transitions of input signals and for outputting transition detection signals corresponding to the transition direction, e.g., from high to low level or from low to high level, a first transistor having a drain coupled for receiving a transition detection signal from the unit blocks, a gate coupled for receiving a first prescribed voltage, and a source coupled for receiving a second prescribed voltage, and an OR-gate for ORing a transition detection signal from the unit blocks and outputting a summation signal.

Abstract: The disclosure is an operation control circuit of a power supply unit in a memory device which outputs a given operation control signal used for supplying a power supply voltage when a main control signal of the memory device is operating and additionally outputs the operation control signal in response to a sub control signal driven when the main control signal does not operate.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: An improved address transition detection circuit prevents malfunctions of a memory by generating an address transition detection signal having a certain pulse width regardless of the width of a pulse of an address signal inputted to a memory. The circuit includes a NOR-gate for NORing an address signal and a chip selection signal, which are externally applied thereto. A level maintaining unit maintains a level of a signal outputted from the NOR-gate for a predetermined time, in accordance with first and second latch signals and first and second delay signals, to output first and second level maintaining signals of different levels. A latch latches the first and second level maintaining signals outputted from the level maintaining unit and outputs first and second latch signals. First and second signal delay units delay first and second latch signals outputted from the latch for a predetermined time and output first and second delay signals.