Abstract: A detector circuit operating in parallel with a bandwidth limited measurement channel in a measurement instrument generates a warning signal when an input signal exceeds a predetermined repetition rate or has a pulse width less than a predetermined value. To provide a warning signal to the measurement instrument that the input signal contains high frequency components that are likely to be missed by the measurement channel, the detector circuit operates in parallel with the measurement channel. A pulse width in the input signal that is sufficiently narrow or a repetition rate that is too high causes the detector to generate the warning signal that is provided to the measurement instrument.

Abstract: A pulse-width-extension circuit for producing an output pulse signal whose pulse width is extended as compared with a pulse width of an input pulse signal when the pulse width of the input pulse signal is equal to or longer than a given width. The pulse-width-extension circuit produces no output pulse signal when the pulse width of the input pulse signal is shorter than the given width.

Abstract: A circuit for eliminating false triggering of a power device in an optically coupled drive circuit caused by dv/dt sensitivity of an optocoupler of the drive circuit comprising a latch circuit having an input coupled to an output of the optocoupler and having an inhibit input; and an inhibit signal generating circuit coupled to an output of the latch circuit for providing an inhibit signal of a preset period of time to the inhibit input of the latch circuit when the output of the latch circuit changes state, thereby inhibiting the passage of any high dv/dt spurious or noise signals to the output of the latch circuit during the preset period of time.

Abstract: A latch circuit is set by a detection circuit which detects a difference between inputs. One of the inputs being delayed by a predetermined period of time. The output of the latch circuit is inverted and delayed through a delay circuit and resets the latch circuit.

Abstract: One embodiment of a circuit and corresponding method for generating a trigger signal upon the occurrence of either set up or hold time violations in the same waveform acquisition produces a trigger signal referenced to, but displaced in time from, the input clock signal. Transitions (13) in a data signal initiate a window pulse (14') whose duration is equal to the sum of a set up time requirement and a hold time requirement. The window pulse is used as the D input to a flip-flop (20) that is clocked by a version of a clock signal whose active edge has been delayed (28) for an interval that corresponds to the hold time requirement. The output of the flip-flop (20) is a trigger signal that only occurs when a set up or hold time violation has occurred. In another embodiment, triggers generated as the result of a set up time violation are referenced to the clock edge, while triggers that are generated as the result of a hold time violation are referenced to a transition in the data signal.

Abstract: A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit.

Abstract: A power-on reset circuit includes a differentiator circuit, a sample-hold circuit and a reset signal generating circuit. The differentiator circuit differentiates a clock signal from an oscillator after a power supply is applied to a power supply terminal. The sample-hold circuit samples a power component only from the output of the differentiator circuit. When the power component exceeds a threshold voltage of the reset signal generating circuit, the reset signal generating circuit generates and provides a reset signal for a logic circuit during a certain period.