Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are used. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crossed over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phases to be generated from the few delay stages.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: A delay circuit for a ring oscillator includes a first electric potential line, a pair of output lines, a pair of two first transistors arranged between the first electric potential line and the pair of output lines, respectively, a second electric potential line, and a pair of two second transistors arranged between the second electric potential line and the pair of output lines, respectively. Respective gates of the first transistors are connected to the pair of output lines, respectively, the first transistors, and the second transistors are connected to each other center-symmetrically, and the output lines are connected to a third electric potential line. Such a circuit can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.

Abstract: A precision wide-range variable delay system whose delay is independent of process, voltage, and temperature variations. A delay controller supplies a voltage, that is independent of process, voltage, and temperature variations, and that is used in a delay line to set the amount of delay through all individual delay elements cascaded together inside of the delay line. The number of cascaded delay elements determines the maximum delay of the delay system. An output voltage controller regulates the output voltage swing of the output from the delay system for stability of the delay over voltage variations. The desired delay from the system is variable and is determined by the user. The pre-delay timing relationships of multiple signals, that are delayed, is maintained by the delay system.

Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3. M4) and the gate biasing transistors (M21, M22).

Abstract: The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof.

Abstract: A variable phase shifting circuit includes a resistance unit and a variable capacitance unit. The resistance unit includes at least one resistor element. The resistance unit input a first signal and a second signal and also output a third signal and a fourth signal. The variable capacitance unit includes two base-to-emitter capacitors of two transistors. The variable capacitance unit is connected to the third signal and the fourth signal. The two base-to-emitter capacitors is varied by controlling collector currents of the two transistors. The third signal and the fourth signal are produced by shifting phases of the first and second signals based on the at least one resistor element and the two base-to-emitter capacitors.

Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Abstract: A voltage-controlled oscillator has a feedback circuit connected to the gate of a transistor which controls a current flowing through an oscillation unit. The feedback circuit applies a voltage depending on the DC voltage of an oscillated signal to the gate of the transistor. When the oscillated signal is reduced in level to lower the DC voltage, the feedback circuit lowers the voltage applied to the gate of the transistor. The current flowing through the oscillation unit is reduced to increase the level of the oscillated signal. When the oscillated signal is increased to increase the DC voltage, the feedback circuit increases the voltage applied to the gate of the transistor. The current flowing through the oscillation unit is increased to reduce the level of the oscillated signal. The feedback process prevents the voltage-controlled oscillator from operating unstably regardless of manufacturing variations of transistors from design values.

Abstract: A voltage controlled oscillator (VCO), for use in a phase locked loop for clock multiplication, for example in recovery of data pulses from a data stream input comprising digital data with unknown phase. According to the invention, the VCO comprises a plurality of VCO stages, each stage being implemented as a differential amplifier. The amplifier load is formed of two cross-coupled gate devices and of two gate devices which are connected as diodes. The differential input is applied to a source coupled input pair as well as to two pull-down gate devices.

Abstract: An input circuit includes a pair of common-base circuits having respective transistors including respective bases to which differential signals transmitted through a transmission line are input and constant current sources connected to the emitters of the transistors, and a level shift circuit for inputting, to the emitters of the common-base circuits, differential signals with anti-phase relation to the differential signals input to the bases of the common-base circuits. This input circuit has lower power consumption and can be used to match impedance.

Abstract: A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emitter resistor of a traditional ring oscillator are replaced by coils (L1 to L6) in all stages.

Abstract: A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches having a first complementary differential current switch and a second complementary differential current switch, the two sets of complementary differential current switches are connected in a push pull arrangement. In this arrangement, the outputs of the first complementary differential current switch of the first set of complementary differential current switches and the first complementary differential current switch of the second set of complementary differential current switches are connected with the input of the second complementary differential current switch of the first set of complementary differential current switches.

Abstract: A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.

Abstract: A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is .alpha. degrees out of phase with the input signal, a second intermediate signal that is .beta. degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal.

Abstract: First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one control circuit to produce increases in the voltage drop across an impedance (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor device) closes to produce a first resultant voltage. The resultant delay in the third switch closure is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit, causing a second resultant voltage to be produced at a fourth switch (e.g. semiconductor device).

Abstract: The delay device 10 includes an ECL gate 11, the current source 16 and two resistive load elements 14, 15 of which are associated with an adjusting circuit 23 producing an adjusting voltage Vd, to cause the polarization current of the current source to vary hyperbolically, and a voltage Vh for keeping constant the voltage at the collectors of the transistors 12 and 13 of the gate 11. The delay device 10 causes the delays between the input signals IN, IN* and output signals OUT, OUT* to vary linearly. The invention is applicable in particular to systems for the transmission of digital data at a very high rate, of more than 1 gigabit per second, for example.