Multiple Outputs With Plurality Of Delay Intervals Patents (Class 327/269)
  • Patent number: 10141915
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9917590
    Abstract: A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 13, 2018
    Assignee: Marvell World Trade Ltd.
    Inventors: Tao Zhang, Xuemei Liu, Hui Wang
  • Patent number: 9906228
    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
  • Patent number: 9875714
    Abstract: A driving circuit includes a receiver configured to receive an image control signal comprising a data signal and a clock signal, separate the data signal from the clock signal and output the separated data and clock signals, a clock recovery unit generating a reference clock signal based on the clock signal and generating a plurality of multi-phase clock signals having different phases from that of the reference clock signal, an output clock generation unit outputting an output clock signal in synchronization with the clock signal and the plurality of multi-phase clock signals, and a data output unit driving a plurality of data lines with a data driving signal corresponding to the data signal in synchronization with the output clock signal, and the output clock generation unit outputs the plurality of multi-phase clock signals.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Han Lee, Taegon Kim, Sunkyu Son
  • Patent number: 9762093
    Abstract: The disclosure features high-resolution pulse-width modulation (HRPWM) controllers that can include a first channel having a first coarse_on register and a first coarse_off register and a counter configured to determine a repetition rate for the first channel. When a coarse_on value of the first coarse_on register and the counter are equal, the first channel can be set “active” and when a coarse_off value of the first coarse_off register and the counter are equal, the first channel can be set “inactive”. The controllers can include a delay line configured to generate a set of delay locked waveforms offset by a fine resolution value and a control module configured to select a delay locked waveform from the set of delay locked waveforms and apply the selected delay locked waveform to the first channel.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 12, 2017
    Assignee: WITRICITY CORPORATION
    Inventor: Bradley Martin
  • Patent number: 9571076
    Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Seo, Sung-Hyun Park, Woo-Jin Rim, Ha-Young Kim, Jae-Ha Lee, Yong-Ho Kim
  • Patent number: 9431958
    Abstract: An apparatus comprises a mechanical resonator-based oscillator module generating a local oscillator signal with a frequency of more than 700 MHz. Further, the apparatus comprises a digital-to-time converter module generating a frequency adapted signal based on the local oscillator signal.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 30, 2016
    Assignee: Intel IP Corporation
    Inventors: Zdravko Boos, Bernd-Ulrich Klepser
  • Patent number: 9395414
    Abstract: A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 19, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Satya Puvvada, Amit Sanghani
  • Patent number: 9397396
    Abstract: The present invention provides a radio system and a method for relaying packetized radio signals. The radio system comprises at least one transmit path, a base band calibration signal generator for generating a base band calibration signal, a digital predistortion unit, a calibration unit and a feedback path. The feedback path is commonly used by the digital predistortion unit and the calibration unit for feeding back a feedback signal. The feedback signal is adapted to update at least one of phase and amplitude changes and the digital predistortion. The present invention further relates to a method for relaying packetized radio signals. The method is capable of updating the digital predistortion as well as adapted for an updating of the phase and amplitude changes. The updating of the digital predistortion and the updating of the phase and amplitude changes is implemented using the feedback signal. The present invention further relates to a computer program product for the manufacture of the radio system.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: July 19, 2016
    Assignee: KATHREIN-WERKE KG
    Inventor: Peter Kenington
  • Patent number: 9188961
    Abstract: A time-to-digital converter (TDC) incorporates a resistor-stabilized delay line, a sampling circuit and a processing circuit. The resistor-stabilized delay line operates to limit the variation in delay values for the delay elements in the delay line due to fabrication process variations. In some embodiments, the resistor-stabilized delay line limits the delay variation of each delay element to a fraction of the delay.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: November 17, 2015
    Assignee: Micrel, Inc.
    Inventor: Bin Liu
  • Patent number: 9024670
    Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 5, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Ashutosh Tiwari, Ish Kumar Dham, Pranav Murthy, Virendra Brijlal Bansal
  • Publication number: 20150097608
    Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashutosh Tiwari, Ish Kumar Dham, Pranav Murthy, Virendra Brijlal Bansal
  • Patent number: 8970276
    Abstract: Circuits and methods are introduced to allow for timing relationship between a clock signal and a synchronization signal to be observed. The observations may include observing the timing relationship between a capture edge of the clock signal and a transition of the synchronization signal. Based on the observations the timing of the synchronization signal transition may be adjusted. Observing the timing relationship may include providing a delayed synchronization signal and a delayed clock signal. The delayed synchronization signal may provide what happens before the capture edge of the clock signal. The delayed clock signal may provide what happens after the capture edge of the clock signal.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 3, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Matthew D. McShea, Scott G. Bardsley, Peter Derounian
  • Patent number: 8941431
    Abstract: There is provided a continuous time cross-correlator comprising: a quantizer for quantizing the incoming signal into discrete levels; a delay line comprising one or more delay units separating a plurality of delay line taps; for each of said delay line taps, a comparator for comparing the signal level of the delay line tap with a correlation value; a continuous time counter for taking the outputs of the plurality of comparators as its inputs, counting the results of the comparisons and outputting the results of the comparisons; and an output comparator for comparing the counter output with a threshold value. The cross-correlator provides for high speed continuous time cross-correlation with low power consumption and a small chip area. Methods of continuous time cross correlation are also provided.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Novelda AS
    Inventors: Kristian Granhaug, Hakon Andre Hjortland
  • Patent number: 8866523
    Abstract: An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: October 21, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ming-Yu Hsieh, Sheng-Che Tseng, Chih-Ming Hung
  • Patent number: 8847810
    Abstract: In a pulse phase difference coding circuit, a count unit includes a plurality of partial counters connected to each other in series so that the most significant bit of an output of the previous stage serves as an operation clock of the subsequent stage. A circulation number detecting unit includes a first latch circuit which is provided for each of the partial counters and latches an output of the partial counter according to a pulse for measurement, and a first delay circuit which treats the partial counter in the second stage or later as an object counter and delays the pulse for measurement by a total delay time in all the partial counters located at the previous stages of the object counter. The pulse for measurement is inputted into the first latch circuit which latches an output of the object counter.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 30, 2014
    Assignee: Denso Corporation
    Inventor: Shigenori Yamauchi
  • Patent number: 8847651
    Abstract: Techniques and mechanisms for operating an integrated circuit to communicate via a hardware interface for the integrated circuit, wherein a pinout with the hardware interface is based on the configuration. In an embodiment, the integrated circuit receives a first plurality of signals via the hardware interface, and sequentially latches a second plurality of signals based on the first plurality of signals. In another embodiment, some or all of the second plurality of signals are variously latched by the integrated circuit in an order which is based on the first configuration.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventor: Michael D. Mirmak
  • Patent number: 8810440
    Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Southeast University
    Inventors: Jianhui Wu, Zixuan Wang, Xiao Shi, Meng Zhang, Cheng Huang, Chao Chen, Fuqing Huang, Xincun Ji, Ping Jiang
  • Patent number: 8797080
    Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Venkatraghavan Bringivijayaraghavan, Jason Brown, Tyler J. Gomm
  • Patent number: 8791764
    Abstract: Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongshin Shin, JaeHyun Park
  • Publication number: 20140176215
    Abstract: To implement a clock skew in an integrated circuit, end-point circuits are grouped into a push group and a pull group based on target latencies of local clock signals respectively driving the end-point circuits. The push group is driven by slow clock gates, and the pull group is driven by fast clock gates. The slow clock gates are determined such that delays of output clock signals are aligned to a base latency. The fast clock gates are determined such that delays of output clock signals are aligned to a minimum pull latency smaller than the base latency. Buffer networks are disposed between the fast and slow clock gates and the end-point circuits such that the local clock signals have the target latencies, respectively.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Suhail AHMED, Ahsan Chowdhury, Brian Millar
  • Patent number: 8760210
    Abstract: A method and system in accordance with the present invention provides for a method and circuit for oversampling using a delay element in which input clock signals and input data signals are affected by phase and time delays to provide for the circuit generating samples providing a greater granularity of detail over a period, thereby reducing error probabilities.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: June 24, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Jeffrey S. Earl
  • Patent number: 8742816
    Abstract: A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 3, 2014
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Publication number: 20140132317
    Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
  • Patent number: 8692602
    Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mao-Hsuan Chou
  • Patent number: 8680907
    Abstract: A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: March 25, 2014
    Assignee: Agere Systems LLC
    Inventors: James D. Chlipala, Scott A. Segan
  • Patent number: 8674741
    Abstract: A delay chain circuit including at least two delay elements, wherein each delay element is configured to: receive a first signal; output a second signal after a delay period; and be operable in at least two modes of operation wherein in a first mode of operation each delay element has a first delay period and in a second mode of operation each delay element has a second delay period.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: March 18, 2014
    Assignee: Nokia Corporation
    Inventors: Petri Antero Helio, Jouni Tapio Kinnunen, Niko Juhani Mikkola, Paavo Sakari Vaananen
  • Patent number: 8653875
    Abstract: Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: February 18, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Morihiko Tokumoto, Masayu Fujiwara, Satoshi Mikami
  • Patent number: 8633722
    Abstract: In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X?1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X?1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: January 21, 2014
    Assignee: Xilinx, Inc.
    Inventor: Andrew W. Lai
  • Publication number: 20140002164
    Abstract: A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.
    Type: Application
    Filed: December 17, 2012
    Publication date: January 2, 2014
    Applicant: SK HYNIX INC.
    Inventor: Choung-Ki SONG
  • Patent number: 8536920
    Abstract: A clock circuit with delay functions includes a first clock tree and a delay module. The first clock tree provides a first clock signal and includes a first clock root and a plurality of first sub-trees. The delay module is coupled to the first clock root or a designated sub-tree among the plurality of first sub-trees for delaying the first clock signal. The delay module includes at least two delay segments, wherein each delay segment includes a delay and a connection net. The delay time caused by each delay segment is substantially the same.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: September 17, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ming-Feng Shen
  • Publication number: 20130214840
    Abstract: A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.
    Type: Application
    Filed: September 13, 2012
    Publication date: August 22, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: HOI JIN LEE
  • Patent number: 8508635
    Abstract: In a solid-state imaging device, each of a plurality of switches is connected between a pulse output terminal of each delay unit and a pulse input terminal of the next-stage delay unit. Each of a plurality of switches is connected between the pulse output terminal and the pulse input terminal of each delay unit. A plurality of switches is turned on and a plurality of switches is turned off in conjunction with an oscillation operation, and a plurality of switches is turned off and a plurality of switches is turned on in conjunction with a holding operation.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 13, 2013
    Assignee: Olympus Corporation
    Inventor: Takanori Tanaka
  • Patent number: 8471736
    Abstract: An automatically calibrating time to digital conversion circuit. The circuit includes a first circuit node for switchably receiving a first calibration signal and a second circuit node coupled with the first circuit node via a first delay path. A third circuit node for switchably receiving a second calibration signal the same as the first calibration signal is coupled with a fourth circuit node via a second delay path. A calibration portion has a third delay path switchably connected with the fourth circuit node and a fourth delay path switchably connected with the second circuit node. The calibration portion generates a delay adjustment signal for adjusting a time delay of the first delay path such that the first time delay combined with the fourth time delay equals the second time delay combined with the third time delay. The calibration portion is disconnected when calibration is not desired for conserving power.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Richard W. D. Booth, Koji Takinami
  • Publication number: 20130141403
    Abstract: To reduce current noise by reducing the current peak value and the current rise slope, a data driver includes a delay unit and a plurality of output circuits. The delay unit sequentially delays a control signal and outputs delay control signals. The output circuits start outputting in response to the delay control signals. The delay unit generates the delay control signals to be output to the output circuits.
    Type: Application
    Filed: November 15, 2012
    Publication date: June 6, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Renesas Electronics Corporation
  • Publication number: 20130057326
    Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 7, 2013
    Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
  • Publication number: 20130038368
    Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.
    Type: Application
    Filed: October 23, 2012
    Publication date: February 14, 2013
    Applicant: SK hynix Inc.
    Inventor: SK hynix Inc.
  • Publication number: 20120306553
    Abstract: A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.
    Type: Application
    Filed: May 2, 2012
    Publication date: December 6, 2012
    Inventors: Sung-Jin Kim, Ji-Hyun Kim
  • Patent number: 8300752
    Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
  • Patent number: 8283960
    Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: October 9, 2012
    Assignee: Oracle America, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
  • Patent number: 8189723
    Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
  • Patent number: 8179180
    Abstract: A device for detecting an approach or a touch related to at least one sensor element, in particular in an electrical appliance, the device comprising an input side and an output side, between which a first signal path with a first input and a first output and a second signal path with a second input and a second output are arranged, wherein the first signal path comprises a delay device with a delay, the delay device configured to delay a digital first input signal at the first input into a digital first output signal at the first output, wherein the delay is dependent on a capacitance value resulting from the approach or the touch related to the sensor element, and wherein the second signal path comprises an XOR-element, which is configured to generate an edge in a digital second output signal at the second output, when the digital first output signal outputted by the delay device exhibits an edge.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: May 15, 2012
    Assignee: PRETTL Home Appliance Solutions GmbH
    Inventor: Dieter Genschow
  • Patent number: 8037372
    Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jeong-Hun Lee
  • Patent number: 8023612
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 20, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth Michael Rose, Matthew Todd Lawson
  • Patent number: 7999591
    Abstract: A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Kim, Jang Jin Nam
  • Patent number: 7977994
    Abstract: A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. In another implementation, a digital pulse-width-modulator with a digital phase-locked loop is also provided.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 12, 2011
    Assignee: The Regents of the University of Colorado, A Body Corporate
    Inventors: Vahid Yousefzadeh, Anthony Carosa, Toru Takayama, Dragan Maksimovic
  • Publication number: 20110164007
    Abstract: Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Applicant: Sony Corporation
    Inventors: Werapong Jarupoonphol, Yoshitoshi Kida
  • Patent number: 7944263
    Abstract: A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit 20 for distributing the clock to timing generating sections 10-1 to 10-n has a clock main path 21 connected to a main path buffer 24 and a clock return path 26 connected to a return path buffer 27. A load capacity of the main path buffer 24 is equal to that of the return path buffer 27. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit 30. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: May 17, 2011
    Assignee: Advantest Corp.
    Inventor: Masakatsu Suda
  • Patent number: 7932765
    Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: April 26, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Ronald A. Kapusta, Doris Lin
  • Publication number: 20110074480
    Abstract: An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: Infineon Technologies AG
    Inventor: Werner Grollitsch