Abstract: An adjustable precision delay circuit includes a series of inverter gates and a multiplexer for selecting any of their outputs or the input to the series. The polarity of the signal input to this circuit is controlled so that any selected output always has the same predetermined polarity, thereby eliminating timing errors arising from factors that vary with the polarity of the output.

Abstract: An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.

Abstract: A pulse width modulation circuit comprises a data register for separating a data pulse signal into a first selection signal and a second selection signal, a delay signal generator for processing the first selection signal and a clock signal to generate a delay signal, and a logic gate circuit for processing the second selection signal, the clock signal, and the clock signal to generate a pulse width modulation data signal.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Abstract: A VCO includes an oscillator and a controller for controlling the operation of the oscillator. The oscillator is formed by connecting odd number of stages of delay circuits in a ring form. The controller creates a second control voltage based on an input first control voltage. The second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference. Each of the delay circuits includes an inverter, first and second current control circuits, and first and second current value setting circuits. The inverter includes a first transistor of first conductivity type and a second transistor of second conductivity type to receive and output a signal. The first current control circuit is connected between the first transistor and the ground, for controlling a current flowing in the first transistor when the first transistor is set in the conductive state according to the first control voltage.

Abstract: A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements.

Abstract: An improved high precision synchronous delay line featuring propagation control circuitry in the voltage controlled delay line removing skew between a pair of propagated waveforms. A pair of waveforms are received by the voltage controlled delay line of the synchronous delay line. The voltage controlled delay line features propagation control circuitry which couples together the propagation of the pair of waveforms through the present invention. If a transition from one level to another level occurs on any one of the received pair of waveforms, the propagation control circuitry prevents the transition from propagating until a corresponding transition occurs on the other one of the pair of waveforms. As a result, any skew that is created between the pair of waveforms, for any reason, is removed by the propagation control circuitry. With the skew removed, the presently improved synchronous delay line features increased precision and provides for greater resolution.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain to be compared with respect to one another. The delay chain is employed within a clock generator circuit that generates internal clock signals of a microprocessor. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. During a test operation when it is desired to test the variable delay units for possible defects, the four delay units are electrically separated from one another by setting the multiplexers in a test mode. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: A digital circuit apparatus having an A/D converter for digitalizing a control voltage which determines the oscillation frequency of an internal clock outputted from a voltage-controlled oscillator, a storing unit for holding a digitalized value, a D/A converter with corrective function for correcting the digital value being held and subjecting the corrected digital value to D/A conversion, and a lock detector for detecting the matching in phase of the internal clock and an external clock. Phase information obtained when the internal clock and the external clock match in phase is held so that, when the generation of the internal clock outputted from the voltage-controlled oscillator is halted and then resumed, the matching in phase of the external clock and internal clock can be achieved in a short period of time.

Abstract: A phase locked loop circuit 11 includes a phase detection circuit 12, a means for phase adjustment, and a recovery circuit 18. The phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means. The phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals. The recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means. The phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means. The circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability.

Abstract: A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138).

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A clocking circuit and clocking method provide a clocking signal that tracks supply voltage VDD such that as supply voltage VDD increases, the signal generation delay also increases. Complementary circuit embodiments and methods are described. In one clocking circuit, a capacitive load stores an amount of charge that varies with supply voltage VDD. A discharge circuit linearly discharges the capacitive load under control of a switch which is responsive to an input signal. A detection circuit is coupled to the capacitive load for detecting linear discharging of the capacitive load to a trigger level V.sub.0 and for providing the clocking signal upon detection of the trigger level. The trigger level is predefined and substantially independent of variation in supply voltage VDD. The clocking techniques presented can be advantageously employed within memory devices such as DRAMs or SRAMs.

Abstract: A method and apparatus for multi-range delay control is disclosed. A method furnishes an output signal (S.sub.K) with a delay that is variable with respect to an input signal (e.sub.0). To enable precise adjustment as a function of a set-point delay (CN) over a plurality of scales, a succession of signals (e.sub.1, e.sub.2, . . . , e.sub.n) delayed with respect to the input signal (e.sub.0) are produced, the delay between a delayed signal (e.sub.2) and the preceding signal (e.sub.1) having a predetermined value. One of the delayed signals (e.sub.2) and a preceding signal (e.sub.1) as selected and a superposition is performed with weighting and an integral effect of the selected signals (e.sub.1, e.sub.2), the selection and weighting being determined as a function of the set-point delay (CN).

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times.

Abstract: A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

Abstract: A delay circuit comprises first modified inverter circuits, a first compensating circuit, second modified inverter circuits and second compensating circuit. Each first modified inverter circuit is composed of a CMOS inverter and an additional NMOS transistor. The CMOS inverter has an NMOS and a PMOS transistor connected in complementary connection between a positive power supply and ground. The additional NMOS transistor controls the current from the first modified inverter circuit to the ground. The first compensating circuit is connected to the gate of each additional NMOS transistor to supply an output signal for compensating a change in characteristic of the additional NMOS transistors. Each second modified inverter circuit is composed of a CMOS inverter and an additional PMOS transistor. The additional PMOS transistor controls a current from the second modified inverter circuit to the positive power supply.

Abstract: A quasi-passive switched capacitor (SC) delay line includes a predetermined number (N) of passive SC delay stages and an amplifier. Each delay stage includes a first transistor having a control terminal for receiving a clock phase, an input terminal for receiving an input signal, and an output terminal, a second transistor having a control terminal for receiving a different clock phase, an input terminal connected to the output terminal of the first switching device, and an output terminal coupled to the amplifier input, and a capacitor coupled between the output terminal of the first transistor and a common supply voltage. The control terminal of each first transistor receives a unique clock phase and the control terminal of the second transistor of the same stage being receives a different clock phase wherein the clock phase received by the second transistor is delayed by two clock cycles from the clock phase received by the first transistor.

Abstract: The use of three identical delay line circuits enables one of said delay circuits to be connected as a minimum delay reference and a second delay circuit to then be continuously compared to said minimum delay reference delay circuit to provide a code which calibrates the second delay line circuit by indicating and controlling continuously the length of the second delay line circuit to provide an exactly 360-degree phase shift of the reference signal under variable temperatures, pressures and voltages. Then, by maintaining the length of the third identical delay line at said determined 360-degree length, and by being able to select any tap output of the third identical delay line circuit responsive to a command, the third delay line circuit provides an adjustable, feedback calibrated, delay line circuit.

Abstract: A variable drive strength buffer circuit is provided that automatically adjusts its associated drive strength to compensate for variations in manufacturing parameters, environmental conditions and operating conditions. As a result, electromagnetic interference, power supply noise, edge rates and ringing may be reduced. The self-adjusting variable drive buffer circuit may be fabricated on an integrated circuit and includes a speed detector unit that measures the relative speed of the integrated circuit. In one embodiment, a self-adjusting variable drive strength buffer circuit includes a circuit speed detector unit having a delay chain consisting of a plurality of variable delay elements. When the delay chain length is matched to the period of an input clock, the length of the chain is an accurate measure of the relative "speed" of the transistors making up the delay chain and therefore of the other transistors on the integrated circuit chip.

Abstract: A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A delay circuit includes a semiconductor chip; a first inverter array formed on said semiconductor chip so as to have a number of first inverters so that it provides a number of delay signals; a second inverter array formed on the semiconductor ship so as to have second inverters, each having the same configuration as that of the first inverters, which are connected to form a ring counter; a phase locked lead-in unit for determining a phase difference between an oscillation output of the second inverter array and a basic clock and converting it into a voltage which is applied as power voltage to the first and second inverter arrays.

Abstract: A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: A synchronous delay line (SDL) for generating delayed signals synchronized with a clock signal is described. The present SDL includes a phase generator and a plurality of serially coupled voltage controlled delay elements. The phase generator takes the clock signal and generates a first trigger signal and a second trigger signal, which are substantially deskewed with respect to each other. Each of the delay elements receives two trigger inputs and outputs a delayed signal and two trigger outputs. The first and second trigger signals are coupled to one of the delay elements as trigger inputs. Each transition of the first and second trigger signals triggers the propagation of two waves through the delay line. The present SDL has a minimum tap-to-tap delay of only one inverter delay, versus a minimum tap-to-tap delay of two NAND gates in prior SDLs. Thus, the present SDL provides for double the number of output taps, and hence, double the resolution as compared to prior SDLs.