Abstract: In an A/D converter circuit, time required for a first pulse signal to have passed through all first delay units of a first pulse delay circuit is defined as first turnaround time, and time required for a second pulse signal to have passed through all second delay units of a second pulse delay circuit is defined as second turnaround time. Average time required for the first pulse signal to pass through any of the first delay units is defined as first passage time, and average time required for the second pulse signal to pass through any of the second delay units is defined as second passage time. A difference between the first and second passage times enables a difference between the first and second turnaround times to be smaller as compared with a reference difference therebetween for a case where the first and second passage times are identical to each other.

Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

Abstract: A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.

Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.

Abstract: A programmable delay structure includes at least one delay stage, each including an inverter connected between input and output nodes, a threshold voltage (VT)-programmable transistor, and a capacitor connectable to the output node through the transistor. During program mode operations, the transistor is programmed to have a low or high VT. During delay mode operation, the gate voltage is set between the low and high VTs. If the transistor has the low VT, the capacitor is connected to the output node and signal delay is increased. If the transistor has the high VT, the capacitor is not connected to the output node and signal delay is not increased. Illustrated embodiments include additional components for facilitating program mode and delay mode operations. Illustrated embodiments also include multiple delay stages where the output node of one stage is connected to the input node of the next. Also disclosed are associated operating methods.

Abstract: A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.

Abstract: An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.

Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.

Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

Abstract: An apparatus to time delay a digital, signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first time delay element has a first input and a first output. The first time delay element is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. An output of the oversampled sensor is connected to the first input of the first time delay element. The second time delay element has a second input and a second output and is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. The first output of the first time delay element is connected to the second input of the second time delay element. A multiplexer has a control input and a multiplexer output. The first output of the first time delay element is connected to a first multiplexer input. The second output of the second time delay element is connected to a second multiplexer input.

Abstract: Semiconductor devices that include test circuitry to measure internal signal wire propagation delays during memory access operations, and circuity configured to store delay information that is used to configure internal delays based on the measured internal signal propagation circuit delays. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a bank logic circuit based on time between receipt of a test command signal directly from the command decoder and a time of receipt of the test command signal routed through the bank logic circuit.

Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.

Abstract: A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

Abstract: A power control semiconductor device includes a voltage control transistor, a control circuit, a bias circuit, and external terminals. The voltage control transistor is connected between a voltage input terminal and an output terminal. The bias circuit generates a voltage that operates the control circuit. Output control signals provided from an outside are input to the external terminals to control an output voltage. The control circuit includes an error amplifier and a logic circuit. The error amplifier outputs a voltage corresponding to a potential difference between a reference voltage and a voltage divided by a voltage divider that divides the output voltage. The logic circuit generates: a signal that changes the divided voltage in accordance with the output control signals; and a signal that stops operation of the bias circuit in response to a combination of the output control signals.

Abstract: There is provided a power supply device including a plurality of battery modules, the battery modules being connected in series with one another according to a gate driving signal from a controller, the power supply device transmitting the gate driving signal from upstream of the series connection toward downstream of the series connection after the gate driving signal is delayed at delay circuits included in the respective battery modules, and returning the gate driving signal to the controller from a most downstream battery module, wherein the power supply device performs malfunction determination of the delay circuits based on a time difference from a transmission time of a signal from the controller to a reception time of the signal.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: DC-DC power converter control comprises current starved delay lines for phase shifting control signals that set and reset a RS flip-flop to provide controllable PWM pulse widths from narrow to wide at a clock frequency. Precise pulse width control and a guaranteed minimum pulse width for pulse frequency modulation (PFM) control the DC-DC power converter during low power demand is also provided. PFM control maintains the same pulse width while decreasing the number of pulses per second when the output voltage exceeds an upper value and increases the number of pulses per second when the output voltage is less than a lower value. Voltage-to-current converters provide control currents to the current starved delay lines that provide the control signals to the SET and RESET inputs of the RS flip-flop. A D-flip-flop may further be used to improved circuit operation when generating high duty cycle (>50 percent) pulse widths.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.

Abstract: According to one or more embodiments of the present invention, a delay circuit includes a first sub-circuit that delays a leading edge of an input signal according to first control settings, the input signal being for an electric device. The delay circuit further includes a second sub-circuit that delays a trailing edge of the input signal according to second control settings. An output signal from the delay circuit is received by the electric device.

Abstract: A motor drive device includes an inverter circuit, a first switching circuit to switch a path between a power supply and the inverter circuit to conduction and interruption, a second switching circuit to switch a path between the inverter circuit and the motor, a current detector to detect a current of the inverter circuit, a controller to, in a case in which a current value of the detected current is not within a predetermined range, output a command voltage which commands switching from the conduction to the interruption, a driver to boost the command voltage input from the controller and output the boosted command voltage to each switching circuit, and a delay circuit disposed between the second switching circuit and the driver to set a timing at which the command voltage is input to the second switching circuit to be later than a timing at which the command voltage is input to the first switching circuit.

Abstract: A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.

Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.

Abstract: A delay circuit and an electronic system equipped with the delay circuit are provided. The delay circuit includes an input terminal, an output terminal, a bias current generator and a delay generator. The bias current generator is coupled between a first reference voltage and a second reference voltage, and is configured to generate a bias current. The delay generator is coupled between the first reference voltage and the second reference voltage, and is configured to generate a delay of the delay signal relative to the input signal according to the bias current. The bias current generator includes a current mirror, a current module and a transistor. The delay generator includes a first current mirror sub-circuit, a second current mirror sub-circuit, a transistor, a capacitor, a switch circuit and a Schmitt inverter, wherein the output terminal is coupled to the Schmitt inverter to output the delay signal.

Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

Abstract: A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

Abstract: An input interface circuit is provided. When a pad voltage is higher than a default operating voltage, a clamping circuit maintains the voltage at a first node at the default operating voltage. A first inverter is coupled between the first node and a second node. A voltage of a third node is adjusted along with the pad voltage (input end of a high-voltage buffering circuit) and the voltage at the second node, and causes the voltage at the third node has a same voltage change trend as the pad voltage. A second inverter is coupled between the third node and a fourth node. A voltage recovery circuit has its input end coupled to the fourth node and its output end coupled to the third node, and selectively couples the third node to a power line or a ground line according to the voltage at the fourth node.

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

Abstract: The present invention teaches a level shift device and a related method. The level shift device contains a first input terminal, a second input terminal, a number of output terminals, and a pulse generation circuit. The first input terminal is for receiving a first pulse input signal. The second input terminal is for receiving a second pulse input signal. The pulse generation circuit cyclically produces pulse output signals, one on each output terminal, according to the first and second pulse input signals. The level shift device further contains a third input terminal for receiving a third pulse input signal. The pulse generation circuit controls the number of pulse output signals produced within each cycle according to third pulse input signal. The present invention is able to produce various numbers of pulse output signals, which is flexible for different applications without investing a new design.

Abstract: A tunable delay circuit includes a first multiplexer, a delay chain, and a second multiplexer. The first multiplexer selects an input signal or a feedback signal as a first output signal according to an enable signal. The delay chain delays the first output signal for different time periods so as to generate a plurality of delay signals. One of the delay signals is used as the feedback signal. The second multiplexer selects one of the delay signals as a second output signal according to a pass signal.

Abstract: Provided is a semiconductor switching device such that there is a reduction in surge or loss in multiple kinds of semiconductor switching element provided in parallel and of differing turn-on/turn-off operation characteristics. The semiconductor switching device includes a switching circuit unit that includes in parallel multiple kinds of semiconductor switching element having different turn-on/turn-off operation characteristics and turns a main current on and off, a driver circuit that includes a current source terminal and a current sink terminal and outputs drive signals that collectively turn the semiconductor switching elements on and off from the current source terminal and the current sink terminal, and an impedance element that is interposed between the current source terminal and the current sink terminal in the driver circuit and causes timings of operations by which the semiconductor switching elements are turned on and off to differ from each other.

Abstract: In a semiconductor device for power management and a semiconductor system including the same, the semiconductor device includes an open loop source generator configured to generate an open loop source, an interface configured to output a dynamic voltage source (DVS) code based on the open loop source, a monitoring unit configured to receive a power supply voltage generated based on the DVS code as a feedback and generate a monitoring signal, and a phase difference measurement unit configured to compare the open loop source with the monitoring signal and set a hold time corresponding to an arithmetic period in a closed loop.

Abstract: Provided is a battery pack, which can prevent a plurality of battery modules from being abnormally assembled. The battery pack may include n battery modules; n slave battery management systems (BMSs) corresponding to the n battery modules, the n slave BMSs respectively and sequentially coupled to each other; and a master BMS coupled to the n slave BMSs. Here, the master BMS is configured to apply a trigger signal to a first slave BMS, the first to (n?1)th slave BMSs are configured to transmit the trigger signal and first to (n?1)th signals, which are different from each other, to a next slave BMS, an nth slave BMS is configured to transmit an nth signal to the master BMS.

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract: A signal compensation circuit includes a first path configured to cause a source signal to pass therethrough and be outputted as a first signal; a delay block configured to output a second signal by delaying the source signal by a predetermined time; a second path configured to cause the second signal to pass therethrough and be outputted as a third signal; and a signal combination block configured to generate a compensated signal by combining the first signal and the third signal.

Abstract: According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits.

Abstract: A shift register unit includes a latch circuit and a transmission circuit. The latch circuit is configured to process a clock signal received by its first clock signal end and a low level signal by a NOR operation to obtain a signal and output the obtained signal when a selection signal is of a high level; during a first time period where the selection signal is of a low level, process a signal outputted by the latch circuit when the selection signal is of a high level by a NOT operation, then process the resultant signal with a feedback signal by a NOR operation to obtain a signal and output the obtained signal; output a low level signal during a time period where the selection signal is of a low level other than the first time period.

Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Abstract: Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot.

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.