Having Specific Passive Circuit Element Or Structure (e.g., Rlc Circuit, Etc.) Patents (Class 327/290)
  • Patent number: 10958198
    Abstract: A system includes an electric motor, at least one pair of high side and low side switches connected to the electric motor, and a microcontroller connected to the high side and low side switches. At least the low side switches have a minimum on-time requirement. The microcontroller controls the switches by outputting a pulse-width modulation (PWM) signal. At least the PWM signal outputted to the low side switch is center-aligned to the off-time. When a request is made to the microcontroller resulting in a low side on-time of zero with a previous duty cycle request that is greater than a predetermined threshold, the microcontroller is constructed and arranged to extend the duty cycle of the low side switch of the at least one pair of switches into the next period to a duration of the required minimum on-time.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 23, 2021
    Assignee: Vitesco Technologies USA, LLC
    Inventors: Benjamin J. Erickson, Lakshmi Narayana Sharma Tejomurtula
  • Patent number: 8885376
    Abstract: A switching regulator IC contains both switching regulator circuitry and an inductor and a capacitor connected in parallel to form a resonant circuit having an associated notch filter frequency response arranged such that, when connected to receive the regulated output voltage, the resonant circuit attenuates the ripple component. This is accomplished by matching the resonant notch to the ripple's fundamental frequency, either manually or automatically. In addition, the resonant circuit's inductor and capacitor can act in concert with decoupling capacitors coupled to the load to form a low pass filter which attenuates harmonics of the ripple's fundamental frequency.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Patrick J. Meehan, Thomas Conway, Aldrick Limjoco, Donal G. O'Sullivan
  • Patent number: 8884689
    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Publication number: 20140266374
    Abstract: Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: SAUDI BASIC INDUSTRIES CORPORATION
    Inventors: Mahmoud N. Almadhoun, Amro Elshurafa, Khaled Salama, Husam Alshareef
  • Publication number: 20140167830
    Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 19, 2014
    Inventors: Weiming Sun, Alvan Lam, Lei Huang, Emma Wang, Peng Zhu
  • Patent number: 8742815
    Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 3, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Sameer Wadhwa, Marzio Pedrali-Noy
  • Patent number: 8674740
    Abstract: The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang Jae Heo
  • Publication number: 20130156131
    Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Anant S. Kamath, Sriram Ramadoss, Shrinivasan Jaganathan
  • Publication number: 20120330873
    Abstract: A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 27, 2012
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Manan SURI, Barbara DE SALVO
  • Patent number: 8264265
    Abstract: An apparatus and methodology for operating an automatic darkening filter (ADF) eye protection device alternately applies an operating voltage to a pair of control terminals of an ADF device circuit in a continuing sequence, where a first polarity voltage is applied to the pair of terminals and then reversed. A delay period is provided between application of the alternating polarities. In some embodiments ground potential is applied to both terminals of the pair of terminals during the delay period.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 11, 2012
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Donald William Greiner, Thomas Joe Hamilton
  • Publication number: 20120212274
    Abstract: A device includes a logic circuit having first, second, and third input ports, a first output port, and a feedback path between the first output port and the third input port. In a first operating state, a logic state change at the first input port triggers a logic state change at the first output port, but a logic state change at the third input port does not trigger a logic state change at the first output port. This allows signals to be routed through the device. In a second operating state, a logic state change of the third input port triggers a logic state change of the first output port. This change is fed back, delayed by a time value, to the third input to maintain an oscillation with at least two edges. The frequency of this oscillation is used to determine a value of a measurement variable.
    Type: Application
    Filed: December 16, 2011
    Publication date: August 23, 2012
    Inventors: Dieter Genschow, Olaf Krause
  • Patent number: 8242577
    Abstract: A fuse of a semiconductor device comprises: a first insulating film formed over a semiconductor substrate; a conductive pattern formed over the first insulating film; a fuse metal formed over the conductive pattern; a contact plug electrically coupling the conductive pattern and the fuse metal; and an energy absorbent pattern formed in the first insulating film and located below an area where the contact plug and the conductive pattern are interconnected. The fuse of the semiconductor device includes a void and a step difference in the lower portion of the contact connected to the fuse pattern. As a result, an energy of a laser applied in the blowing process is absorbed in the void or the step difference, which does not affect peripheral patterns, thereby preventing defects.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun Ho Shin
  • Publication number: 20120133409
    Abstract: A delay circuit used in a schedule controller includes a voltage detection unit, a timer, and a first electronic switch. The voltage detection unit receives an input voltage and compares the input voltage with a predetermined voltage. The timer is controlled by the voltage detection unit to calculate duration of an interval time. The first electronic switch is switched on or off under the control of the timer. When the input voltage substantially equals or exceeds the predetermined voltage, the timer calculates duration of the interval time, the timer generates and transmits a switch signal to the first electronic switch when the timing is reached, and the first electronic switch is switched on by the switch signal and provides an output voltage.
    Type: Application
    Filed: January 17, 2011
    Publication date: May 31, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: MING-CHIH HSIEH
  • Patent number: 8154324
    Abstract: A driver integrated circuit for driving at least one high voltage half bridge stage. The driver including a filter circuit for filtering a signal provided to the half bridge stage, a minimum pulse width of the signal being near a constant time of the filter, wherein the filter circuit prevents distortions introduced when the signal is at its minimum pulse width from being passed to the half bridge stage.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: April 10, 2012
    Assignee: International Rectifier Corporation
    Inventors: Christian Locatelli, Giovanni Galli
  • Patent number: 7982516
    Abstract: A programmable delay element with a variable delay generator employs feed forward and feedback control signals to corresponding feed forward and feedback control elements integrated within the variable delay generator. The variable delay generator is responsive to a control signal. The variable delay generator uses transfer switches to couple reactive circuit elements to a signal node in accordance with the control signal. The feed forward element couples a fixed voltage to corresponding nodes of the feed back element. The feedback element completes a bypass circuit to apply the fixed voltage to the signal node once the programmable delay element has delayed a source signal. The feed forward element is responsive to a buffered version of the source signal. The feedback element is responsive to a buffered version of the output of the delay element. A corresponding method for reducing frequency induced delay variation in a programmable delay element is disclosed.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 19, 2011
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventor: Gerald Lee Esch, Jr.
  • Patent number: 7872602
    Abstract: A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: January 18, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yi-Lin Chen
  • Publication number: 20100188128
    Abstract: An initial pulse signal is split into a first pulse signal and a second pulse signal. The first pulse signal is delayed through a first impedance to generate a first delayed pulse signal. The first impedance attenuates the first delayed pulse signal to generate an attenuated pulse signal. The second pulse signal is delayed through a second impedance to generate a second delayed pulse signal. The first delayed pulse signal and the attenuated pulse signal are combined to generate the two-pulse response signal.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 29, 2010
    Inventors: Haw-Jyh Liaw, Shwetabh Yerma
  • Patent number: 7733148
    Abstract: Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier, the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-seuk Kim
  • Publication number: 20100090741
    Abstract: A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3, a capacitor element 4 and a connection wiring 6. The connection wiring 6 includes a first polysilicon layer 13a above a substrate 10, and a first silicide layer 14a which connects the resistance element 3 and the capacitor element 4 and is on the first polysilicon layer 13a. The capacitor element 4 includes a diffusion layer 12b in the surface region of the semiconductor substrate 10, a gate insulating layer 15b on the diffusion layer 12b, a second polysilicon layer 13b on the gate insulating layer 15b, and a second silicide layer 14b on the second polysilicon layer 13b. The resistance element 3 includes a third polysilicon layer 13c above the semiconductor substrate 10. The first, second and third polysilicon layers 13a, 13b and 13c are integrally provided. The first and second silicide layers 14a and 14b are integrally provided.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 15, 2010
    Inventor: Hiroyuki TAKAHASHI
  • Publication number: 20100039155
    Abstract: A time delay circuit for providing a time delay to a reset circuit includes a first circuit, a second circuit, an AND gate and a control signal input. The first circuit includes a first resistor and a first capacitor. The second circuit includes a second resistor and a second capacitor. The AND gate includes a first input, a second input and an output. The first capacitor includes an input coupled to a power source via the first resistor, and an output grounded. The second capacitor includes an input coupled to the control signal input and an output grounded. The first input of the AND gate is coupled to the input of the first capacitor, the second input coupled to the input of the second capacitor, and the output configured for coupling to a integrated circuit to reset.
    Type: Application
    Filed: December 4, 2008
    Publication date: February 18, 2010
    Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.
    Inventor: JUNG-LIN CHANG
  • Publication number: 20100019820
    Abstract: A low power monolithic CMOS device incorporating functions to control power supply transition noise such as in audio circuits and systems. The digital control circuit incorporates MOSFETs that are maintained in an OFF state during normal operation and are turned ON only when system power is turned on or off to thus eliminate the need for bias voltages and maintain minimal quiescent current.
    Type: Application
    Filed: January 23, 2008
    Publication date: January 28, 2010
    Inventors: Venkatesh P. Pai, Mohammad Rehman, Umesh Jayamohan
  • Publication number: 20100007398
    Abstract: A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Inventors: Shengyuan Zhang, Shoujun Wang, Yong Wang
  • Publication number: 20090284291
    Abstract: A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N?1) of inverters. A delay circuit composed of a first resistance element and a capacity element is arranged in series between two inverters in the second transmission path so as to correspond to any one of the inverters in the first transmission path. The capacity element is formed by a capacitive inverter having the same input capacity ratio as the any one of the inverters. The complementary signal generation circuit generates output signals having the logic levels which are complementary to each other through the first and second transmission paths.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kazuhiro TERAMOTO
  • Patent number: 7586352
    Abstract: A converter includes a time-delay circuit for a PWM signal, applied to input of the time-delay circuit, by which rising edges of the PWM signal are delayed by an ON delay and falling edges of the PWM signal are delayed by an OFF delay, in order to form a drive signal, available at the output of the time-delay circuit, for a semiconductor switch element. The time-delay circuit includes two resistors, two capacitors, a diode and a comparator, and is therefore particularly easy to implement.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: September 8, 2009
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Norbert Huber
  • Patent number: 7456664
    Abstract: The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: November 25, 2008
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Harald Jacobsson, Spartak Gevorgian, Thomas Lewin
  • Patent number: 7456670
    Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: November 25, 2008
    Assignee: The Regents of the University of California
    Inventors: Ravindran Mahanavelu, Payam Heydari
  • Patent number: 7446583
    Abstract: Switching arrangement for interconnecting electrolytic capacitors that comprises an electronic switch formed by a semiconductor device and a delay member. The semiconductor device has a control input which is, through an RC-type delay member, connected to a control input (VS) supplying the switching signal. The switching arrangement has a predetermined switching delay. The semiconductor device is a field effect transistor (FT), whose main circuit is coupled through an inductive element (L), supplying a second delay, to the capacitor (C1) to be switched. The inductive element (L) is a conductor (10) of determined length surrounded by a high-frequency ferrite core (11, 12). The delay effected by the RC member ensures only that fraction of the switching delay at which the device is loaded within its permissible load limit and the remaining delay is supplied by the inductive element (L).
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: November 4, 2008
    Inventor: András Fazakas
  • Patent number: 7446585
    Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: November 4, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
  • Publication number: 20080169826
    Abstract: A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 17, 2008
    Inventor: James E. Bartling
  • Publication number: 20080157844
    Abstract: A time delay circuit includes an RC circuit with a resistor and a capacitor connected, and a switch. The switch includes a first terminal, a second terminal, and a control terminal for controlling conduction of the first and second terminals. The first terminal is connected to an end of the resistor, which is connected to the capacitor. The second terminal is connected to ground, and the control terminal is connected to the other end of the resistor configured for receiving an input signal. When the input signal changes from logical low to logical high to turn off the switch, the capacitor is charged to a predetermined value with a predetermined rise time beginning from the change of the input signal. When the input signal changes from logical high to logical low to turn on the switch, the first and second terminals of the switch conduct to quickly discharge the capacitor to the predetermined value substantially synchronized with the change of the input signal.
    Type: Application
    Filed: June 21, 2007
    Publication date: July 3, 2008
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: ZE-SHU REN
  • Publication number: 20080150604
    Abstract: A converter includes a time-delay circuit for a PWM signal, applied to input of the time-delay circuit, by which rising edges of the PWM signal are delayed by an ON delay and falling edges of the PWM signal are delayed by an OFF delay, in order to form a drive signal, available at the output of the time-delay circuit, for a semiconductor switch element. The time-delay circuit includes two resistors, two capacitors, a diode and a comparator, and is therefore particularly easy to implement.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 26, 2008
    Inventor: Norbert HUBER
  • Patent number: 7154324
    Abstract: Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: December 26, 2006
    Assignee: Altera Corporation
    Inventors: Simardeep Maangat, Sergey Y. Shumarayev
  • Patent number: 7057435
    Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 6, 2006
    Assignee: Regents of the University of California
    Inventors: Ravindran Mahanavelu, Payam Heydari
  • Patent number: 6801073
    Abstract: The present invention is a system, circuit and method for low voltage operable, small footprint delay. The delay circuit of the present invention uses an input switching configuration with a limited gate to source conductance to enhance the delay time for any given resistor and capacitor area in an RC network. According to the delay circuit of the present invention, the output of the RC network transitions very slowly in order to achieve a long delay. When the next stage of the delay circuit trips, the limited gate to source conductance is bypassed to allow rapid full rail presetting or resetting on the output of the RC network. This rapid full rail presetting or resetting limits power consumption and rapidly prepares the delay circuit for the next edge transition or cycle. Methods and systems incorporating the delay circuit and techniques of the present invention are also disclosed.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: October 5, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 6784713
    Abstract: In order to ensure safe and reliable time-delayed signal outputting with a simple redundant structure of a circuit arrangement, a common actuating element acts on two timers with associated A/D converters. In this case, the time delay which is predetermined by the actuating element and is relevant for the outputting of the switching signal is determined by forming the difference between a total resistance, detected by measurement, and a first resistance element, detected by measurement. This is followed by a comparison of the difference, which reflects second resistance elements that is determined by computation, with a second resistance element which is determined by measurement. The switching signal is then output with a time delay when there is a match between the second resistance element determined by measurement and that determined by computation.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: August 31, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Herbert Haller, Harald Schurz
  • Patent number: 6753716
    Abstract: The present invention relates to a circuitry for impedance matching. The invention utilizes circuitry for impedance matching, which circuitry for example is connected to a differential or balanced power amplifier or some other device in need of output impedance tuning. The circuitry includes at least one inductance connected to at least one device which conducts when being forward biased, and a direct current (DC) source controlling the conduction of the device. The circuitry eliminates the DC component of a signal passing through it. By controlling the device that is conducting when it is forward biased, it is possible to turn the circuitry on and off, thus altering the impedance at the output of the amplifier. Hence, a load switch has been created at the output of the amplifier.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: June 22, 2004
    Assignee: Nokia Corporation
    Inventors: Henrik Sihm, Jesper Riishöj
  • Patent number: 6741122
    Abstract: An improved method and design for adjusting clock skew in a wire trace is disclosed. Aspects of the invention include a corrugated pattern wire trace bracketed by a pair of parallel conducting wire frames with wire extensions projecting between the corrugations of the wire trace. The wire frames are connected to a voltage supply. The transmission properties of the wire trace, and thus the degree of clock skew associated with the wire trace, are affected by the number of wire extensions protruding between the corrugations, their degree of penetration, as well as other factors inherent in the design. The present design can achieve the same degree of clock skew with a smaller surface area covered and with fewer resistive losses than with prior art designs.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: May 25, 2004
    Assignee: LSI Logic Corporation
    Inventors: Ashok K. Kapoor, Lei Lin
  • Publication number: 20030234674
    Abstract: The present invention is a system, circuit and method for low voltage operable, small footprint delay. The delay circuit of the present invention uses an input switching configuration with a limited gate to source conductance to enhance the delay time for any given resistor and capacitor area in an RC network. According to the delay circuit of the present invention, the output of the RC network transitions very slowly in order to achieve a long delay. When the next stage of the delay circuit trips, the limited gate to source conductance is bypassed to allow rapid full rail presetting or resetting on the output of the RC network. This rapid full rail presetting or resetting limits power consumption and rapidly prepares the delay circuit for the next edge transition or cycle. Methods and systems incorporating the delay circuit and techniques of the present invention are also disclosed.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventor: Donald M. Morgan
  • Publication number: 20030218489
    Abstract: An input circuit for an HF-transmitting component 1 of a battery-operated device for the transmission of a data signal aims to reduce the power consumption. For that purpose the fundamental frequency of a reference oscillator 5 is modulated with the digital data signal, the data rate being greater than 20 kchip/s. For smoothing of the modulated reference signal an amplitude limiter 11 and a band pass filter 15 are connected between the reference oscillator 5 and the HF-transmitting component 1.
    Type: Application
    Filed: May 19, 2003
    Publication date: November 27, 2003
    Applicant: Diehl AKO Stiftung & Co. KG
    Inventors: Marc Sebald, Jurgen Zimmermann, Wolfgang Werner
  • Patent number: 6629289
    Abstract: In a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, there are determined first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal and a second waveform slew data of the second signal to the object logic cell. A first portion of a first waveform of the first signal and a second portion of a second waveform of the second signal is calculated in time then it is determined whether the first portion of the first waveform overlaps the second portion of the second waveform.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 30, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Miyuki Yamamoto, Tetsuya Akimoto
  • Patent number: 6462623
    Abstract: An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: October 8, 2002
    Assignee: Parthus Ireland Limited
    Inventors: John M. Horan, John G. Ryan, Mark M. Smyth, David J. Foley
  • Patent number: 6456137
    Abstract: First and second wires are disposed adjacent to each other. Even pairs of buffers and inverters are disposed on the wires. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Lengths of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Gaps between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: September 24, 2002
    Assignee: NEC Corporation
    Inventor: Kazuki Asao
  • Patent number: 6414531
    Abstract: In order to provide a more flexible adjustment of signal delay times in a circuit configuration containing a line device and a number of electronic components accessing it, it is proposed to add additional capacitances, which can be varied in a controllable manner. In addition, the capacitances are to formed in a region of the existing components.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: July 2, 2002
    Assignee: Infineon Technologies AG
    Inventor: Martin Brox
  • Patent number: 6346842
    Abstract: A variable delay path circuit having delay paths of different lengths is disclosed. Any of the delay paths can be selected to match the operating conditions of the system. In one embodiment of the invention, a delay path circuit having two delay paths connects a driver and receiver. Each of the two delay paths contains sites at both ends for placing zero ohm resistors, solder or copper slugs. To select one of the two delay paths, zero ohm resistors, solder or copper slugs are placed in the sites at the ends of the desired delay path. The delay is then dictated by the time it takes for a clocking signal to travel the length of selected delay path.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: February 12, 2002
    Assignee: Intel Corporation
    Inventors: Stephen H. Hall, Jr., Maynard C. Falconer
  • Patent number: 6344763
    Abstract: A semiconductor integrated circuit device includes a plurality of data input/output terminals to transmit send/receive a plurality of input/output data signals to/from an external source, a mode set circuit to set an operation mode of the semiconductor integrated circuit device and generating a plurality of capacitance set signals according to a combination of externally applied control signals, and a plurality of variable capacitance circuits respectively provided between a predetermined reference potential and a plurality of data input/output terminals, capable of changing independently the capacitance according to a capacitance set signal.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: February 5, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kengo Aritomi, Takayuki Miyamoto
  • Patent number: 6137353
    Abstract: An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: October 24, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Peter Stroet, Rishi Mohindra
  • Patent number: 6005435
    Abstract: A high-voltage generating circuit includes a high-voltage production circuit, a high-voltage detecting circuit, and a control circuit. The high-voltage detecting circuit has a high-voltage circuit section to which a voltage of 1 kV to several tens of kilovolts is applied and a low-voltage circuit section to which a voltage of several tens of volts is applied. In the high-voltage circuit section, a parallel circuit formed of a first voltage-dividing resistor and a part of a second voltage-dividing resistor and a speed-up capacitor, and another parallel circuit formed of the remaining part of the second voltage-dividing resistor and a third voltage-dividing resistor and another speed-up capacitor are connected in series to form a two-stage parallel circuit.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: December 21, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunobu Saida, Nobuaki Imamura, Yasuhiko Toda, Haruo Takahashi, Masaru Omura, Hisashi Takiguchi
  • Patent number: 5959480
    Abstract: Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and second inverter chains, each having a plurality of series-connected inverters. A first signal, which may be a digital logic signal, is applied to an input of the first inverter chain. A second signal, which may be a clock signal used to latch the logic signal in an integrated circuit, is applied to an input of the second inverter chain. The inverter chains may be constructed such that the inverters of the second chain have a stronger drive capability than the corresponding inverters of the first chain. Capacitive coupling is provided between outputs of inverters of the first chain and outputs of corresponding inverters of the second chain.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: September 28, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Masakazu Shoji
  • Patent number: 5936475
    Abstract: A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emitter resistor of a traditional ring oscillator are replaced by coils (L1 to L6) in all stages.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: August 10, 1999
    Inventors: Nikolay Tchamov, Petri Jarske
  • Patent number: 5828258
    Abstract: A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: October 27, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Tomoya Kawagoe, Hideto Hidaka, Mikio Asakura