Having Specific Passive Circuit Element Or Structure (e.g., Rlc Circuit, Etc.) Patents (Class 327/290)
  • Patent number: 5714899
    Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: February 3, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Sylvie Wuidart, Tien-Dung Do
  • Patent number: 5598111
    Abstract: A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: January 28, 1997
    Assignee: NEC Corporation
    Inventor: Toshio Enomoto