Abstract: An active damping circuit for an electromagnetic interference (EMI) filter for power factor correction (PFC) circuit is provided which simulates a line damping impedance which actively varies according to sensed line current. The active damping circuit comprises an nth-order, Cauer-Chebyshev, low-pass filter having input series damping impedance (Z.sub.d) simulated with a power operational amplifier and high-frequency isolation transformer. The simulated damping impedance offers greatly reduced size and power dissipation as compared to prior art passive schemes which typically require large impedance components for damping. A passive damping circuit is also shown which involves providing an alternate inductive current path in parallel with a damping resistor whereby lower frequency currents are diverted through the alternate current path and higher frequency currents continue to flow through the damping resistor.

Abstract: The invention relates to a control circuit for a semiconductor switch, comprising a transformer coupling (T1, T2) for generating AC voltage signals including both control energy and control information, a rectification coupling (DB1, DB2) for rectifying the AC voltage signals generated by the transformer coupling (T1, T2) for generating DC voltage levels (U1, U2, U3) appropriate for turning on and turning off a semiconductor switch (SW1), a first resistor (R2) connected at its first end to a driving electrode of the semiconductor switch (SW1), a second resistor (R1) connected between the driving electrode and the emitter or source electrode of the semiconductor switch, and a booster semiconductor switch (V1) provided between the driving electrode of the semiconductor switch (SW1) and an DC voltage output (U3) generated by the rectification coupling and intended for turning off the semiconductor switch, the driving electrode of the booster semiconductor (V1) being connected to a DC voltage output (U2) generate

Abstract: An improved gate drive circuit for use with a switching power device in a power converter and other power-transfer type circuits and the like is described. The gate drive circuit according to the present invention requires fewer components and space that convention prior art gate drive circuits. The drive circuit provides isolation between the control circuitry and the device without storing a significant amount of long-term (i.e., D.C.) energy and is also more energy efficient than many prior art gate drive circuits. Additionally, the present invention comprises means for cleanly terminating the drive signal to the switching power device when the control circuitry terminates operation. This prevents an incorrect signal to the switching power device, which may conduct at an inappropriate time, causing damage to the power converter or power-transfer circuit. Many prior art drive circuits have D.C.

Abstract: A modulator for producing repetitive short high voltage pulses is provided. The modulator includes a high voltage power supply, a plurality of pulse forming networks each capable of being charged to a potential equal to twice the voltage of the high voltage power supply, and a plurality of switches interconnecting the pulse forming networks. The switches have a first state connecting the pulse forming networks in parallel with the high voltage power supply to charge the pulse forming networks, and a second state connecting the pulse forming networks in series to discharge the pulse forming networks into a load. The pulse forming networks are charged by use of a resonant charging technique. The modulator further includes an input configured to receive a triggering pulse, the triggering pulse causing the switches to change from the first state to the second state.

Abstract: The present disclosure illustrates that the process of summing an amplitude limited PSK (phase-shift keyed) signal with a one data bit delayed version of that signal and envelope detecting the sum will produce a digital binary data stream that is representative of the original data used to produce the PSK signal in the first place. This approach is distinguished over the prior art approach in that the PSK signal is limited to an amplitude value which is less than the minimum value produced by vectorial summation of noise with the transmitted PSK signal for optimal bit error rate performance.