Using Diode Type Nonlinear Devices Only Patents (Class 327/314)
  • Patent number: 10770452
    Abstract: Apparatus and methods for electrical overstress (EOS) protection circuits are provided herein. In certain configurations, an EOS protection circuit includes an overstress sensing circuit electrically connected between a pad and a first supply node, an impedance element electrically connected between the pad and a signal node, a controllable clamp electrically connected between the signal node and the first supply node and selectively activatable by the overstress sensing circuit, and an overshoot limiting circuit electrically connected between the signal node and a second supply node. The overstress sensing circuit activates the controllable clamp when an EOS event is detected at the pad. Thus, the EOS protection circuit is arranged to divert charge associated with the EOS event away from the signal node to provide EOS protection.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 8, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Leslie Paul Wallis
  • Patent number: 10340851
    Abstract: An apparatus includes a differential cascode amplifier including a first transistor and a second transistor. The apparatus further includes a transistor including a source terminal coupled to a gate terminal of the first transistor of the differential cascode amplifier. The transistor also includes a drain terminal coupled to a gate terminal of the second transistor of the differential amplifier.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Alan Ngar Loong Chan, Gareth Seng Thai Yeo
  • Patent number: 10217734
    Abstract: In a semiconductor device, a control circuit controls a potential difference of a switching element between a first terminal connected to a power source node and a second terminal connected to a first reference node. A first clamping circuit is connected between the first terminal and a control terminal of the switching element and is energized by a voltage equal to or higher than a first clamp voltage. A second clamping circuit is connected between the control terminal and the first reference node and clamps the potential difference to a second clamp voltage lower than the first clamp voltage. A third clamping circuit is connected between the control terminal and the second terminal. The control unit activates the second clamping circuit when a load current is equal to or greater than a predetermined threshold voltage, and activates the third clamping circuit after a predetermined time period elapses.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 26, 2019
    Assignee: DENSO CORPORATION
    Inventor: Jun Fukuhara
  • Patent number: 10186954
    Abstract: A voltage converter and a control circuit thereof are provided. The control circuit includes a voltage status comparator and a control signal generator. The voltage status comparator receives an input voltage and an output voltage, and provides a base voltage. The voltage status comparator compares voltage values of the output voltage and the input voltage or compares voltage values of the output voltage and the base voltage according to a voltage status of the input voltage, and generates a comparison result. The voltage status comparator generates a bias voltage according to the comparison result. The control signal generator generates a control signal according to the bias voltage and transmits the control signal to a control terminal of a driving switch, where the driving switch is turned on or cut off according to the control signal.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 22, 2019
    Assignee: Excelliance MOS Corporation
    Inventors: Ching-Tsan Lee, Ke-Wei Wu, Ming-Hung Chien
  • Patent number: 9911610
    Abstract: A method for manufacturing a semiconductor device includes providing a wafer having a first semiconductor layer, forming at the first semiconductor layer a contact layer which includes a metallic chemical element, and implanting ions of a first chemical element different to the metallic chemical element into the contact layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Patent number: 9887675
    Abstract: A power amplifier includes: a transistor having a gate electrode, a source electrode and a drain electrode; a passive component part connected to the gate electrode through a gate wiring; and a harmonic circuit connected between the source electrode and the gate wiring and disposed in a region between the gate electrode and the passive component part and between the source electrode and the gate wiring.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takao Haruna
  • Patent number: 9209799
    Abstract: A fourth n-channel MOSFET has a source terminal and a back-gate terminal connected to each other. A switch element is connected between the source terminal of the fourth n-channel MOSFET and a ground potential, and the source terminal of the fourth n-channel MOSFET is made become the ground potential when the fourth n-channel MOSFET is OFF. A protection circuit is provided between a connection node of the source terminal of the fourth n-channel MOSFET and an input terminal of the switch element, and the ground potential so that a negative inflow current from the drain terminal of the fourth n-channel MOSFET caused by electrostatic discharge flows to the ground potential.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: December 8, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Kouichi Yamada
  • Publication number: 20140300401
    Abstract: The present invention is a method by which diodes are connecting in a circuit such that they are more robust. The method involves placing two diodes of opposite directions in parallel and applying a DC bias such that a forward diode may then handle higher than normal voltages and a reverse diode provides a failsafe in the event of a reverse bias.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 9, 2014
    Inventor: Joshua D. Kaggie
  • Patent number: 8729558
    Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi
  • Patent number: 8710894
    Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 29, 2014
    Assignee: Infineon Technologies AG
    Inventors: Christian Arndt, Veli Kartal, Rainald Sander
  • Patent number: 8677166
    Abstract: A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heon-Hee Lee, Hoi-Jin Lee
  • Patent number: 8466731
    Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: June 18, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nang Ping Tu, Chun Hao Liao
  • Patent number: 8457246
    Abstract: An apparatus and method for amplifying a Transmit (Tx) signal according to an Envelope Tacking (ET) scheme in a wireless communication system are provided. A transmitting end apparatus includes an envelope gain controller for controlling a gain of a digital baseband Tx signal in accordance with power control, a detector for detecting an envelope signal from the digital baseband Tx signal whose gain is controlled, and for shaping on the envelope signal, a first Digital to Analog Converter (DAC) for converting the shaped envelope signal into an analog signal, and an envelope modulator for generating a drain bias of a power amplifier that amplifies a Radio Frequency (RF) Tx signal by using the analog envelope signal. Accordingly, a digital-based ET scheme is implemented, and by using a plurality of shaping tables, efficiency of the ET scheme can be maximized in a transmitting end that uses power control.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Shin-Ho Kim, Hyung-Weon Park
  • Patent number: 8440061
    Abstract: A device for use with an RF generating source, a first electrode, a second electrode and an element. The RF generating source is operable to provide an RF signal to the first electrode and thereby create a potential between the first electrode and the second electrode. The device comprises a connecting portion and a current sink. The connecting portion is operable to electrically connect to one of the first electrode, the second electrode and an element. The current sink is in electrical connection with the connection portion and a path to ground. The current sink comprises a voltage threshold. The current sink is operable to conduct current from the connecting portion to ground when a voltage on the electrically connected one of the first electrode, the second electrode and the element is greater than the voltage threshold.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 14, 2013
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Ed Santos
  • Patent number: 7952407
    Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 31, 2011
    Assignee: Ideal Industries, Inc.
    Inventor: Huaibin Yang
  • Patent number: 7741884
    Abstract: A load drive circuit which can operate at high speed with low consumption current while performing the gate-to-source over voltage protection for its load driving field-effect transistor. A Zener function device is connected between the gate and the source of the load driving field-effect transistor, and an on/off-switch circuit to supply either on-potential or off-potential to the gate of the field effect transistor is provided. The current flowing through the Zener function device when the load driving field-effect transistor is conductive is limited by the on/off-switch circuit.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: June 22, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Norihiro Kawagishi, Kazuyoshi Asakawa
  • Patent number: 7729453
    Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: June 1, 2010
    Inventors: Bing Li, David Wolf, James Plesa, Lakshman S. Tamil
  • Patent number: 7443703
    Abstract: A semiconductor device has a semiconductor element connected to an input/output terminal and a reference voltage terminal, a first rectifier element connected between the input/output terminal and the reference voltage terminal, which performs rectifier operation to prevent a voltage of the input/output terminal from becoming higher than a voltage of the reference voltage terminal by a predetermined value or more, and a second rectifier element connected between the input/output terminal and the reference voltage terminal, which performs rectifier operation to prevent the voltage of the reference voltage terminal from becoming higher than the voltage of the input/output terminal by a predetermined value or more.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: October 28, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Inukai, Yukihiro Urakawa
  • Patent number: 7298213
    Abstract: An input impedance matching circuit for a low noise amplifier includes a source pad, a gate pad, an input transistor, a source degeneration inductor and a matching capacitor. The gate pad receives an input signal and the input transistor amplifies the input signal transmitted from the gate pad. The source degeneration inductor electrically coupled to an external ground voltage is adapted for input impedance matching of the low noise amplifier. The source pad is coupled to a source electrode of the input transistor and the matching capacitor is formed between the gate pad and the source pad extending the source pad to be disposed under the gate pad. Accordingly, impedance matching of the low noise amplifier may be facilitated and the gain and noise figure of the low noise amplifier may be improved.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Hoon Kang
  • Patent number: 7129759
    Abstract: The power IC includes an output transistor M0 which controls a current flowing into an L load, a dynamic clamp circuit which clamps an overvoltage, and a clamp control circuit which controls the operation of the dynamic clamp circuit. The clamp control circuit activates the dynamic clamp circuit, which is normally inactive, upon detection of a back EMF by the L load.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: October 31, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Ikuo Fukami
  • Patent number: 7030677
    Abstract: A method and circuits to improve the stability of low dropout voltage regulators having an adaptive biased driving stage. Said improvement of stabilization is valid through the total range of output current possible. A serial impedance is added to the gate capacitance of the PMOS pass device of said LDO. Said serial impedance could be a resistor or a transistor. In case of low load currents said impedance is not dominating, for high load currents said impedance keeps the gate pole close to the resonance frequency of the output tank. In case of medium load currents, wherein the inner resistance of the driving stage is about equal to said serial impedance, the gate pole could get too low. This problem is solved by reducing said serial impedance by shunting. Said shunting can be performed stepwise depending on the size of the load current.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: April 18, 2006
    Assignee: Dialog Semiconductor GmbH
    Inventor: Axel Pannwitz
  • Patent number: 6947337
    Abstract: Random-access memory device having select lines, bit lines, and several RAM cells, each RAM cell being connected to a corresponding one of said select lines and to a corresponding one of said bit lines. The random-access memory device further having select buffers for selecting the read-out of one out of the selected lines when receiving a selection signal. Each of the select buffers having an inverter serving as driver. The inverter is being followed by a diode for limiting output voltage swings at the respective select line.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 20, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Nikola Stojanov
  • Patent number: 6927996
    Abstract: A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The control of such spurious voltages improves device operating margins and allows the construction of larger arrays.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 9, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James R. Eaton, Jr., Kenneth J. Eldredge
  • Patent number: 6894567
    Abstract: An improved method is presented for adding ESD protection to large signal MOS circuits. Each of the ESD and the MOS devices are separately connected off chip to rigid voltage points, thereby eliminating additional capacitive loading of MOS devices. An improved RF MOS amplifier is presented which implements the method of the invention. An ESD device, comprising back to back diodes, is connected to the Vdd and GND nodes off chip, thus insulating the amplifying transistor from any performance degradative interaction with the ESD device due to transient forward biasing. The method and apparatus are easily extended to circuits comprising any number of MOS devices.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: May 17, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Vathulya Vickram, Govil Alok, Sowlati Tirdad
  • Patent number: 6847248
    Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: January 25, 2005
    Assignee: Broadcom Corporation
    Inventor: Janardhanan S. Ajit
  • Patent number: 6777996
    Abstract: A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cathode connected to the input/output node (12); a third diode (D3) connected between the cathode of the first diode (D1) at a first node (14) and the anode of the second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode of the first diode at first node (14); a second arrangement for supplying a second potential at the anode of the second diode at second node (16); a first capacitor (C1) connected between the cathode of the first diode at first node (14) and ground; and a second capacitor connected between the anode of the second diode at second node (16) and ground.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: August 17, 2004
    Assignee: Raytheon Company
    Inventor: Marlin C. Smith, Jr.
  • Patent number: 6636118
    Abstract: In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series is connected between the collector and emitter of each HBT. The p-side is connected to the collector side, and the n-side is connected to the emitter side. A protection circuit in which pn junction diodes of the number equal to or smaller than that of the pn junction diodes are connected in series is connected between the base and the emitter. The p-side is connected to the base side, and the n-side is connected to the emitter side. With the configuration, in the case where an overvoltage is applied across the collector and emitter due to a fluctuation in load on the antenna side, the collector terminal is clamped by an ON-state voltage of the protection circuits, so that the HBT can be prevented from being destroyed.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: October 21, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Cyushiro Kusano, Eiichi Hase, Hideyuki Ono, Osamu Kagaya, Yasunari Umemoto, Takahiro Fujita, Kiichi Yamashita
  • Patent number: 6529059
    Abstract: An integrated circuit including a transistor having a first electrode coupled to an output bond pad and a second electrode coupled to a reference potential, such as ground bond pad. A degeneration device is coupled between the second electrode and the reference potential. A diode is coupled between the second electrode of the transistor and the reference potential with the anode of the diode coupled to the second electrode reference potential and the cathode of the diode coupled to the reference potential for an NPN transistor.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: March 4, 2003
    Assignee: Agere Systems Inc.
    Inventor: Paul Cooper Davis
  • Patent number: 6518815
    Abstract: A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the source terminal. The protection circuit has a resistance variable between a first value and a second value according to the operating condition of the power device. In a first embodiment of the protection circuit, an ON-OFF switch made by means of a horizontal MOS transistor has a control terminal connected to the drain terminal of the power device. In a second embodiment of the protection circuit, the ON-OFF switch is replaced with a gradual-intervention switch made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal of the power device.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: February 11, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Grimaldi, Luigi Arcuri, Salvatore Pisano
  • Patent number: 6501319
    Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: December 31, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hidehiro Takata
  • Patent number: 6483365
    Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: November 19, 2002
    Assignee: NEC Corporation
    Inventor: Yasuyuki Morishita
  • Patent number: 6462601
    Abstract: An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: October 8, 2002
    Assignee: Faraday Technology Corp.
    Inventors: Hung-Yi Chang, Yi-Hua Chang
  • Patent number: 6437626
    Abstract: A “PN junction element ta which produces the Peltier effect and Seebeck effect within the same element and imparts a noise reducing effect,” which prevents an adverse influence of white noise included in an AC waveform to be supplied from a commercially available AC power supply or a parasitic noise or the like caused by electromagnetic interference on an electromagnetic device that is supplied with power and which is effective when attached at the designing or manufacturing stage to each “low-power” functional circuit which provides a later-attached or externally-attached device is adapted to a “high-power” circuit.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: August 20, 2002
    Inventor: Kazuo Ohtsubo
  • Patent number: 6414532
    Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 2, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hung Der Su, Jian-Hsing Lee, Yi-Hsun Wu, Mau-Lin Wu
  • Patent number: 6404261
    Abstract: A switch circuit for battery-powered equipment, for example a mobile telephone or a portable computer, comprises a 4-terminal bi-directional semiconductor switch (M1) and a protection diode (Dbg). The switch (M1) has a control-gate terminal (g) for applying a control signal (Vg) to form a conduction channel (12) in a body region (11) of the switch, for turning the switch (M1) on and off between a battery (B) and a power line (2) of the equipment. The switch (M1) also has a back-gate terminal (b; bg) in a bias path that serves for applying a bias potential (Vmin) to the body region (11). The protection diode (Dbg) has a diode path in series with the back-gate terminal (b; bg) so as to provide in the bias path a rectifying barrier (25; 25′) that blocks current flow between the body region (11) and the gate-bias terminal (b, bg) in the event of a reverse voltage polarity across the switch (M1), for example when recharging the battery (B).
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: June 11, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond J. Grover, Franciscus ACM Schoofs, Pieter G. Blanken
  • Patent number: 6404574
    Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected, respectively to the head nodes and the emitters of first and second upper drive transistors. The diodes increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Raymond E. Barnett
  • Patent number: 6400204
    Abstract: An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled the input bond pad and a second electrode coupled to the ground bond pad. There may be other circuit elements between the emitter and the ground bond pad. At least two series coupled diodes are coupled between the input bond pad and the ground bond pad. The at least two series coupled diodes provide ESD protection to the transistor and circuit coupled between the input bond pad and the ground bond pad.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: June 4, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Paul Cooper Davis
  • Patent number: 6396331
    Abstract: A compensation circuit for minimizing undesirable effects of parasitic components, such as a parasitic capacitance of a controlled electronic device (e.g., transistor) is coupled in parallel with the controlled electronic device in a manner that is effective to decrease the spurious AC signal-coupling of the parasitic component, such that the amplitude of the unwanted AC noise voltage across the load element is very significantly reduced, or effectively minimized. The parametric values of the transfer function of the electronic device in the by-pass compensation circuit are such as to attenuate the unwanted AC noise voltage across the load, by a factor that approximates the amplitude of the spurious signal, thereby effectively minimizing its unwanted contribution to the load voltage.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: May 28, 2002
    Assignee: Intersil Americas Inc.
    Inventor: Leonel Ernesto Enriquez
  • Patent number: 6388516
    Abstract: Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different power supply in a closed loop feedback servo system. A clamping network connected to the higher gain amplifier to avoid hard saturation due to transient feedback signals from a reactive load, especially an inductive load, also prevents hard saturation of the high voltage, high current amplifier. An adjustable feedback circuit connected to the higher gain amplifier allows adjustment to obtain critical damping of a second order system and faster response to achieve proportionality of output current to input voltage with an accuracy of very few parts per million error and with minimum settling time.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: May 14, 2002
    Assignee: International Business Machines Corporation
    Inventors: Samuel K. Doran, William A. Enichen
  • Patent number: 6388496
    Abstract: The present invention relates to a semiconductor output circuit that protects a circuit including such a reverse operation as reverses the potentials of a collector and an emitter of a bipolar transistor. A cathode of a protective diode is connected to a P type side of a base-emitter PN junction of a bipolar transistor constituting a semiconductor output circuit, while an anode of the protective diode is connected to an N type side of the base-emitter PN junction. By positively operating the bipolar transistor in a reverse direction with a reverse current gain &bgr;R>1, a reverse voltage between a collector and an emitter of the bipolar transistor is precluded from exceeding Veco to prevent the transistor from being broken down due to its reverse operation.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Tsurumi, Toshiro Kubota
  • Patent number: 6377120
    Abstract: A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: April 23, 2002
    Assignee: Pixart Imaging Inc.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 6359490
    Abstract: The purpose of the present invention is to provide a clamping circuit which has a simple circuit design, with which the clamping voltage range can be easily adjusted, and which can operate at reduced power consumption, as well as interface circuit that makes use of the clamping circuit. NMOS transistor NT1 and diode D1 are connected in series between the feed line of power source voltage Vcc and input terminal Tin, and diode D2 and PMOS transistor PT1 are connected in series between input terminal Tin and ground voltage GND. The divider voltages VND1, and VND2 obtained from resistive elements R1, R2 and R3 connected in series are applied to the control terminals of transistors NT1 and PT1, respectively. Also, transistor NT2 is connected in parallel to resistive element R2. By means of control voltage VB input to the control terminal of NT2, the divider voltages are controlled, and the range of the clamping voltage can be controlled.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: March 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Seisei Oyamada
  • Patent number: 6339356
    Abstract: A variable attenuator formed from a combination of PIN diodes is provided. The PIN diodes may be coupled in a “T,” “p” or other appropriate configuration. At radio frequencies (RF), a PIN diode acts as a variable resistor with a resistance value based on the bias current of the PIN diode. To control the attenuation level of the variable attenuator, the bias current of the PIN diodes are selectively adjusted. Digital values relating to selected bias currents, and thus selected attenuation levels, are stored in a memory. These digital values are provided as control signals that set the bias current levels for the PIN diodes. The bias current levels control the attenuation level of the variable attenuator.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: January 15, 2002
    Assignee: ADC Telecommunications, Inc.
    Inventors: Earl A. Daughtry, Roy Charles Reese
  • Patent number: 6333661
    Abstract: An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock signal supplied from the first clock line, a second clock line formed on the insulating substrate to input a signal obtained from the clock buffer to a shift register serving as a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first clock line to remove electrostatic charge from the first clock line, and a second protection diode circuit connected to the second clock line to remove electrostatic charge from the second clock line.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Ando, Yoshiro Aoki, Masaki Miyatake
  • Publication number: 20010045858
    Abstract: An active snubber circuit having a controllable dV/dt. The circuit includes a power device and surface mount components including a resistor having a value selectable to control the dV/dt. The use of surface mount components achieves a low profile, small size circuit that can advantageously be used to eliminate noise generated by contact arcing, to dissipate arc energy while clamping to a predetermined voltage value, and in power conversion applications to provide a desirable dV/dt, among other applications.
    Type: Application
    Filed: February 2, 2000
    Publication date: November 29, 2001
    Inventor: Aiman Alhoussami
  • Publication number: 20010023962
    Abstract: A semiconductor chip is ESD protected, in part, by utilizing floating lateral clamp diodes. Unlike conventional clamp diodes, which are based upon parasitic bipolar devices associated with large MOS transistors, the floating lateral clamp diodes utilize a well formed in the substrate as the cathode, and a plurality of regions of the opposite conductivity type which are formed in the well as the anode.
    Type: Application
    Filed: September 30, 1998
    Publication date: September 27, 2001
    Inventor: RONALD PASQUALINI
  • Patent number: 6288590
    Abstract: The present invention provides an improved high voltage protection integrated circuit (IC) input buffer. An IC includes a number of circuit elements and an input pin. Each of the circuit elements can tolerate a process dependent maximum voltage magnitude. The input pin can be provided with a voltage magnitude that is larger than the process dependent maximum voltage magnitude of individual circuit elements. The circuit elements include a subset of internal circuit elements and a subset of input buffer circuit elements. The input buffer circuit elements couple the internal circuit elements to the input pin, and are intercoupled in accordance with a predetermined topology to accept the larger voltage magnitude provided to the input pin without damaging the circuit elements.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: September 11, 2001
    Assignee: Intel Corporation
    Inventor: Bal S. Sandhu
  • Patent number: 6278326
    Abstract: A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: August 21, 2001
    Assignee: Texas Instruments Tucson Corporation
    Inventors: Kenneth W. Murray, Joel M. Halbert
  • Patent number: 6275089
    Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: August 14, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jun Song, Ting Cheong Ang, Shyue Fong Quek, Lap Chan
  • Patent number: 6271706
    Abstract: The present invention provides an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a central node. The de-coupling circuit further includes a PMOSFET transistor and a NMOSFET transistor that have their gates coupled at the node. The PMOSFET and NMOSFET transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 7, 2001
    Assignee: Intel Corporation
    Inventor: Raj Nair