Abstract: A DC/DC converter includes a soft start overshoot prevention mechanism. The DC/DC converter includes a DC/DC conversion circuit, an overshoot detection apparatus, a pulse width modulation generator, an error amplifier, and an integration circuit connected to an output port of the error amplifier. The integration circuit is configured to perform integration processing on a difference between a reference voltage and an output voltage of the DC/DC conversion circuit, and control an amplitude of an amplified voltage that is input by the error amplifier to the pulse width modulation generator. The overshoot detection apparatus obtains an operating status parameter of the DC/DC converter, and controls, when the operating status parameter of the DC/DC converter meets an operating status parameter requirement, the integration circuit to discharge.

Abstract: Disclosed herein is an apparatus that includes a first reference voltage generator configured to generate a first voltage, a second reference voltage generator configured to generate a second voltage, a detection circuit configured to compare the first voltage with the second voltage to generate a selection signal, and a selection circuit configured to select one of the first and second voltages responsive to the selection signal. The detection circuit is configured to have a hysteresis property in changing a state of the selection signal.

Abstract: An electronic barrier device, includes an Isolating Barrier or a Zener Barrier, with a voltage limiter or voltage shunt such as at least one zener device for voltage limitation in a circuit during a fault condition. The barrier device includes a crowbar device arranged to latch across the at least one voltage shunt device to reduce power dissipation in the at least one voltage shunt device in the circuit fault condition. The crowbar device is arranged to latch responsive to a change in a current flowing in the barrier device.

Abstract: An apparatus and method for determining an alignment of a codeword is disclosed. A data stream may be received, and a cumulative syndrome value determined. The cumulative syndrome value may be based on error correction and data scrambling operations performed on the data stream. If the cumulative syndrome value matches a predetermined cumulative syndrome value, then alignment of the codeword with respect to the data stream is determined.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Abstract: A signal switching apparatus includes a signal control switch, a switch circuit, a blocking capacitor and a surge current dissipating circuit. The signal control switch coupled between a first signal transceiving end and a second signal transceiving end is turned on or turned off according to a first control signal. The switch circuit having at least one first transistor is controlled by a second control signal to be turned on or off, and a first end of the switch circuit is coupled to the first signal transceiving end. The blocking capacitor is coupled between a second end of the switch circuit and a reference voltage terminal. The surge current dissipating circuit having at least one second transistor is coupled between the second end of the switch circuit and the reference voltage terminal. The second transistor is configured to dissipate a surge current and also turned off when operated normally.

Abstract: A voltage detector comprising: a first voltage reference generator for generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the second voltage reference signal is higher than the first voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal; and a switch for selectively, connecting the input of the trigger to the first or second voltage reference signal, wherein the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the voltage detector is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the voltage detector is high, and a voltage detector system for monitoring an input signal and outputting a detecti

Abstract: Various embodiments of the present disclosure provide an inverter circuit, a driving method, an array substrate, a detecting method, and a display apparatus, which may enable a simple structure by incorporating a switch transistor with a resistor. The simple structure is configured to make the levels of a signal at an outputting terminal of the inverter circuit and a signal at an inputting terminal of the inverter circuit being opposite.

Abstract: A switch circuit includes FETs including a first FET group including m FETs, a second FET group including n FETs at a position away from the input terminal than the first FET group, and an intermediate FET between the first FET group and the second FET group, and capacitive elements including m capacitive elements, n capacitive elements, and an intermediate capacitive element, the capacitive element (C1i) (i is an integer between 1 and m inclusive) is connected in parallel to i consecutive FETs of the first FET group starting from a top closer to the input terminal, the capacitive element (C2j) (j is an integer between 1 and n inclusive) is connected in parallel to j consecutive FETs of the second FET group starting from a top closer to the input terminal, and the intermediate capacitive element is connected in parallel to the intermediate FET.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

Abstract: In at least one general aspect, an apparatus can include a first field effect transistor (FET) device and a second FET device. The apparatus can include a characterization circuit coupled to the first FET device and the second FET device where the characterization circuit can be configured to characterize a responsiveness of each of the first FET device and the second FET device. The apparatus can include a balancer configured to produce a modified gate drive signal for the first FET device based on the responsiveness of the first FET device.

Abstract: A vehicle powertrain includes a monolithically integrated load switch, mirror switch, and temperature array, and a gate driver. The gate driver includes a first comparator configured to filter a current level of the mirror switch, and a second comparator configured to provide a reference to the first comparator based on temperature array output such that a gate discharge rate of the switch, enabled by the first comparator, varies proportionally with a temperature adjusted filtered current level.

Abstract: In one aspect, a device includes a first power switch having a first gate, a second power switch paralleled with the first power switch and having a second gate, a gate driver to output a gate drive signal to drive both the first gate and the second gate, a first conduction path to couple the gate drive signal to the first gate, a second conduction path to couple the gate drive signal to the second gate, and a distribution choke to distribute the gate drive signal to the first and second power switches. The distribution choke has a first winding disposed in the first conduction path and a second winding disposed in the second conduction path. The distribution choke is coupled in a differential mode.

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

Abstract: A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.

Abstract: Disclosed examples include a transient event detector circuit to detect transient events in a switching converter, including a DLL circuit to detect changes in a duty cycle of a pulse width modulation signal used to operate a switching converter, and an output circuit to provide a status output signal in a first state when no transient event is detected, and to provide the status output signal in a second state indicating a transient event in the switching converter in response to a detected change in the duty cycle of the pulse width modulation signal.

Abstract: A circuit applied to a display apparatus includes a front-end circuit, a conversion circuit and an impulsive interference detection circuit. The front-end circuit converts an analog input signal into a digital input signal. The conversion circuit, coupled to the front-end circuit, converts the digital input signal from a time domain to a frequency domain to generate a frequency-domain signal. The impulsive interference detection circuit, coupled to the conversion circuit, detects a noise intensity of the frequency-domain signal to generate a detection result, which is used to determine whether the analog input signal has impulsive interference.

Abstract: Methods and apparatus for equalization of a high speed serial bus. A well-tuned passive equalization circuit for use with high frequency differential signals suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

Abstract: A discharge circuit applied in a motherboard includes a platform controller hub (PCH), a first electronic switch, a second electronic switch, and first capacitor. A control terminal of the first electronic switch is coupled to a standby pin of the PCH. A second terminal of the first electronic switch is coupled to the standby power. A control terminal of the second electronic switch is coupled to the second terminal of the first electronic switch. A second terminal of the second electronic switch is coupled to a first power source through a resistor coupled with a capacitor in parallel. The standby pin of the PCH outputs a digital low signal, to control the first electronic switch is turned off rapidly, and the second electronic switch is turned on. A voltage of the first power source is discharged through the resistor rapidly.

Abstract: A MOSFET active-disable switch is configured to clip an incoming signal in opposing directions when in an off state. By one approach the clipping is symmetrical and accordingly the switch clips both positive and negative peaks of the incoming signal. In many application settings it is useful for the clipping to serve to decrease a predetermined kind of resultant distortion such as even order distortion. In the on state this MOSFET active-disable switch is configured to not clip the incoming signal in opposing directions.

Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Abstract: An electrostatic discharge (ESD) protection control circuit for an output pad of an integrated circuit includes an output driver and a control switch. The output driver, coupled to the output pad, includes a first output transistor for outputting power or signals to the output pad. The control switch, for improving ESD protection on the output pad when closed, includes a first connection terminal, coupled to a gate terminal of the first output transistor; a second connection terminal, coupled to a ground terminal; and a control terminal, coupled to a first power supply terminal.

Abstract: In the present invention, a main switch circuit (13) is provided between an electric power line (PL), to which voltage outputted from a solar cell (11) is applied, and a battery module (12). A protection circuit (19) turns OFF the main switch circuit (13) to protect the battery module (12) from overcharging when the voltage (VBAT) of the battery module (12) is equal to or greater than an upper limit voltage. The voltage outputted from the solar cell (11) is set so as to be greater than the upper limit voltage to allow the battery module (12) to be charged to the upper limit voltage. When a charge ON command signal has been received, a control unit (18) turns ON only a sub-switch circuit (14) to introduce current from the solar cell (11) into a parallel circuit (15) and to suppress the voltage (VPL) of the power line (PL) to less than the upper limit voltage before turning ON the main switch circuit (13).

Abstract: A variable attenuator comprises a series resistance, and an adjustable shunt resistance, wherein the adjustable shunt resistance comprises a series circuit of a fixed resistor and a semiconductor element having an adjustable resistance.

Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.

Abstract: A method includes generating an input voltage for an operational amplifier from a received electromagnetic signal in a receiver unit by an input resistance and generating an output voltage by the operational amplifier by a fixed amplification factor. The input voltage is changed until the output voltage lies within a predefined interval that includes the value of the reference voltage. The input voltage is tapped at a divider node of a voltage divider. The gate voltage of the MOS transistor, operating within a nonlinear range and connected to the divider node, is changed to adjust the output voltage to the reference voltage such that a forward resistance of the transistor is changed nonlinearly. A field strength value received by the receiver unit is determined from a comparison of the value of the present gate voltage with quantities assigned to stored gate voltage values.

Abstract: A method and system for signal reception and processing, and more particularly for reducing the effects of random additive impulse interference is provided.

Abstract: A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract: An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

Abstract: An integrated circuit device comprising at least one electrostatic discharge (ESD) clamp device. The at least one ESD clamp device comprises a first channel input, a second channel input, and a control input arranged to receive a control signal. The at least one ESD clamp device is arranged to selectively operate in a conductive state in which the at least one ESD clamp device permits current to flow between the first and second channel inputs thereof based at least partly on the received control signal. The integrated circuit device further comprises at least one biasing module. The at least one biasing module comprises at least one output operably coupled to the control input of the at least one ESD clamp device, and at least one input arranged to receive a thermal regulation signal. The at least one biasing module being arranged to apply a bias to the control signal for the at least one ESD clamp device based at least partly on the received thermal regulation signal.

Abstract: A self ESD protected RF transistor. The RF transistor is connected to a sub-circuit which causes the RF transistor to self-protect from ESD damage. The sub-circuit triggers the RF transistor to clamp a positive polarity ESD pulse to ground/emitter terminal. The sub-circuit also shunts a negative polarity ESD pulse to ground.

Abstract: An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.

Abstract: An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.

Abstract: There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices; a second signal transferring unit including a plurality of second switching devices; a first shunting unit including a plurality of third switching devices; and a second shunting unit including a plurality of fourth switching devices.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: An optimized pseudo-random period pattern can reduce audible noise in a system that includes an inverter circuit configured to provide power to an electric machine. A system can include a PWM optimization module (POM) comprising the PPP. A carrier period for a carrier signal used to provide PWM inverter drive signals can be selected in accordance with the PPP. The PPP can be expressed as an array of 200-400 elements, each element a period belonging to a finite set of 2 or more predetermined periods. A period can be selected by index from the array, and the index incremented to progress through the PPP, which can be repeated upon its completion. The PPP can be optimized to reduce audible noise while mitigating inverter losses. Modeling techniques can determine the number of array elements, the number of possible periods, and the period values that optimize the PPP.

Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: Input/output (I/O) line driving circuits are provided. The circuit includes a first I/O line driver and a second I/O line driver. The first I/O line driver receives a first input signal in response to an enable signal to generate a first control signal and drives a first I/O line in response to a second control signal. The second I/O line driver receives a second input signal in response to the enable signal to generate the second control signal and drives a second I/O line in response to the first control signal.

Abstract: According to an embodiment, an FET drive circuit includes an FET, a first circuit, a resistor and a third rectifying device. The first circuit includes a first rectifying device, a second rectifying device and a capacitive element sequentially provided in series from a drain to a gate of the FET, the first rectifying device allowing a forward electric current flowing from the drain to the gate, and the second rectifying device having a predetermined breakdown voltage with respect to the electric current from the drain to the gate. The resistor is provided between a power source and a connecting point of the second rectifying device and the capacitive element; and the third rectifying device provided between a source and a gate of the FET.

Abstract: A clamping circuit includes a clamping element with a control terminal and a load path that is coupled between a first circuit node and a second circuit node. A control circuit is coupled between the first circuit node and the second circuit node and is also coupled to the control terminal of the clamping element. The control circuit includes at least one snap-back unit with two load terminals and is only coupled between the first circuit node and the control terminal of the clamping element. The snap-back unit has an electrical resistance between the two load terminals and is configured to reduce the electrical resistance when a voltage between the two load terminals reaches a given threshold value.

Abstract: A system that drives multiple MOSFETs in parallel for direct current and alternating current solid state power controller applications may include networks connected to the gates of the MOSFETs to protect the MOSFETs from being damaged during high current interruption. For direct current applications, the system may include a switching protection and damping network and a gate drive balancing network. For alternating current applications, the system may include two switching protection and damping networks and a gate drive balancing network.

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.

Abstract: An exemplary embodiment of the present invention relates to an active damper and a driving method thereof. An AC input passed through a dimmer is transmitted to an active damper through a rectification circuit. The active damper includes a damper resistor connected to the rectification circuit, a damper switch connected to the damper resistor in parallel, and a delay circuit delaying a turn-on time of the damper switch by a predetermined initial period from a turn-on time of the dimmer.

Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.

Abstract: This invention provides a common mode noise cancellation circuit for the unbalanced signals. The unbalanced signals come from a signal source with a first signal terminal and a second signal terminal having a first grounding potential. The common mode noise cancellation circuit comprises a grounding terminal and a subtractor. The grounding terminal with a second grounding potential is electrically coupled to the second signal terminal of the signal source through an impedance unit. The subtractor comprises a first receiving terminal, a second receiving terminal and a signal output terminal. The first receiving terminal and the second receiving terminal are electrically coupled to the first signal terminal and the second signal terminal respectively for receiving the unbalanced signals. The subtractor subtracts the noise coming from the first receiving terminal and the noise coming from the second receiving terminal to reduce the output noise of the signal output terminal.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.