Abstract: A protecting apparatus for protecting an isolation circuit between different power domains receives a first signal, which is a level-changeable signal, from a first power domain and outputs a second signal to the isolation circuit. The apparatus includes an anti-noise circuit and a signal shaper. The anti-noise circuit receives the first signal. The signal shaper receives the output of the anti-noise circuit and outputs the second signal to the isolation circuit.

Abstract: The present invention relates to a circuit for controlling waveform distortion resulting from nonlinearity of the impedance of a control terminal (gate or base) capacitance of a transistor, which can be employed in circuits showing a nonlinearity performance of high frequency amplifier or oscillator. According to the circuit of the invention, the waveform distortion can be properly controlled to improve the efficiency of power conversion in a high frequency circuit employing FET, regardless of the frequency band, while assuring a favorable matching of input for the circuit. Also, it can provide the reliability of an integrated circuit by employing outside voltage control circuit. Moreover, it can be fabricated on a wafer substrate of FET circuit with an inexpensive cost, which affords unrestricted designing of the circuit.

Abstract: A diode circuit of the present invention comprise an input/output terminal connected to the transmission line, a power supply terminal connected to the power supply, a plurality of diodes connected in series between the input/output terminal and the power supply terminal and a capacitive element having one end connected to a connected point of the plurality of diodes and the other end connected to the ground. In the input/output terminal, an applied signal from the transmission line exceeds the predetermined potential, it is clamped to the predetermined potential by the plurality of diodes connected in series. At the connecting points among a plurality of diodes and the input/output terminal, vibration of potential is reduced by the capacitance element.

Abstract: An improved voltage clamp for operating with wireless communication input circuits over the RF band. The clamp provides for symmetrical clamping for excessive positive and negative input voltage excursions. The clamp does not exact a current penalty when operating in the non-excessive positive and negative input voltage regimes. The clamp is comprised of an input node, a capacitor, a MOS transistor, a diode and a ground potential node.

Abstract: Circuitry for amplifying a single-ended analog sensor output includes a field effect transistor (FET) having a gate connected to a first end of a capacitor, the second opposite end of which is connectable to the sensor output. The gate of the FET is also connected to a first end of a resistor and to a cathode of a diode. The anode of the diode, the opposite end of the resistor and the drain of the FET are connectable to a ground reference, and the source of the FET defines an amplifier output that is connectable to a constant current source. The capacitor, resistor and diode are operable to bias the FET to thereby prevent clipping of the output signal at the amplifier output. A high-pass filter is also provided at the second end of the capacitor, and a number of diodes are preferably included for providing for amplifier input protection, electrostatic discharge protection and output DC overvoltage protection.

Abstract: The input circuit of the present invention includes an NMOSFET. One terminal of the NMOSFET is connected to an input terminal and the gate of the NMOSFET is connected to a power supply terminal via a clamping circuit. A signal, received at the one terminal of the NMOSFET with an amplitude equal to or larger than that of a power supply voltage, is output through the other terminal of the NMOSFET with an amplitude equal to that of the power supply voltage. The input circuit further includes: a gate controller, which is connected to the other terminal of the NMOSFET; and a PMOSFET. One terminal of the PMOSFET is directly connected to the other terminal of the NMOSFET and the gate of the PMOSFET is also connected to the other terminal of the NMOSFET via the gate controller. If the voltage at the other terminal of the NMOSFET is at a high level, the gate controller turns the PMOSFET ON. Alternatively, if the voltage at the other terminal of the NMOSFET is at a low level, the gate controller turns the PMOSFET OFF.

Abstract: The invention describes a circuit layout for generating a supply DC voltage in a dependent relationship to a non-constant input DC voltage in three voltage intervals, with the supply voltage being maintained at a constant nominal value in the intermediate voltage interval, and with the supply voltage being reduced by constant differential values in the other two voltage intervals in order to allow emergency functions to the maintained; implementation is effected by means of a diode arrangement for the first differential value, by means of a first Zener diode arrangement for maintaining the constant value, and by means of a second Zener diode arrangement for bridging the diode arrangement. In addition, a process will be described for generating an output voltage with superimposed current pulses for a signal generator unit which process will feed in such a supply voltage via a control circuit. The circuit layout according to this invention is particularly suitable for implementing this process.

Abstract: An isolation method and circuit for providing dc isolation between two circuits that may have different reference potentials. There is provided a control circuit having an output terminal for providing a reset signal of predetermined length on the output terminal. A circuit to be controlled having an input terminal is provided, the circuit to be controlled being reset when a signal on the input terminal is below a predetermined threshold. A capacitor is coupled between the output terminal and the input terminal, the plate of the capacitor directly coupled to the circuit to be controlled being normally at a relatively high voltage. A voltage source is coupled to the input terminal of the circuit to be controlled through the parallel combination of a resistor and circuitry for unidirectional transmission of current toward the voltage source, generally a diode.

Abstract: A circuit (12) for reducing positive ground bounce effects on an integrated circuit (10) of the type having an integrated circuit transistor (40) that has reduced conduction when exposed to a positive ground bounce potential includes circuitry responsive to an increase in ground potential to produce a drive current and circuitry for applying the drive current to the integrated circuit transistor (40) to oppose the reduced conduction. The positive ground bounce circuit (12) has a ground bounce sense transistor (56) of same conductivity type as the integrated circuit transistor (40), and a circuit (69) to bias the ground bounce sense transistor (56) normally into conduction to pass a control current. Since ground bounce sense transistor (56) also has reduced conduction when exposed to a positive ground bounce potential, a diode (72) is provided to redirect the control current to the integrated circuit transistor (40), thereby reducing the effects of a positive ground bounce condition.

Abstract: A field device electrostatic discharge protective circuit is described. The field device electrostatic discharge protective circuit comprises an N-type FET, an NMOS, an impedance device and a resistor. The gate and the drain of the N-type FET connect to the input port. The drain of the NMOS connects to the internal circuit. The source of the NMOS connects to ground. The gate of the NMOS connects to the source of the N-type FET. The impedance device is set between the source of the N-type FET and the ground. The resistor is set between the drain of the N-type FET and the drain of the NMOS.

Abstract: In an address electrode drive circuit of a plasma display panel, clamping diodes which yield a small forward voltage drop and have a fast switching speed are connected between the output terminal of the drive circuit and the power source and between the output terminal of the drive circuit and the ground. A backward current and voltage dashing from the load to the output transistors of the drive circuit are initially bypassed and absorbed with the clamping diodes and subsequently bypassed and absorbed with parasitic diodes of the output transistors, and the drive circuit is protected against the incoming surge current and voltage.

Abstract: A SUB wiring provided outside of a common discharge line formed on outer periphery of a chip in parallel to the latter. To the common discharge line, only voltage clamping elements and diode elements as electrostatic protection elements are connected. The common discharge line is in floating condition for rising withstanding voltage. On the other hand, to the SUB wiring, additional circuits, such as BBG circuit and so forth, consisting of transistors are connected to connect the latter to the substrate. With these two wirings, the width of the common discharge line can be made narrower to limit an increase of a chip area. By this, it is possible to improve resistance to electrostatic breakdown without increasing chip area.

Abstract: A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.

Abstract: A circuit and apparatus for generating a light pulse from an inexpensive light-emitting diode (LED) for an accurate distance measurement and ranging instrument comprises an LED and a firing circuit. An optional pre-biasing circuit provides a reverse-bias signal to the LED to ensure the LED does not begin to emit light before a firing circuit can provide a sufficiently high current pulse of short duration as a forward current through the LED. The LED is driven by the firing circuit with a pulse of high peak power and short duration. The resulting light pulse from the LED can be inexpensively used to derive distance and ranging information for use in a distance measurement and ranging device.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A switching circuit has switching elements for passing-through or cutting-off signals of a positive pulse, which is a rectangular pulse rising from a low level and falling after having kept a high level for a certain time as a high voltage input signal, and a negative pulse, which is a rectangular pulse falling from a high level and rising after having kept a low level for a certain time, the switching circuit being applied to a capacitive load driving device.

Abstract: The present invention concerns a transmission circuit of an audio/video data bus that includes a clamp connected between first and second output terminals of the transmission circuit; biasing networks for respectively biasing the output terminals during one operational mode of the transmission circuit; and switched biasing networks for respectively biasing the output terminals during a second operational mode of the transmission circuit; the switched biasing networks being controlled by a digital input signal, wherein a circuit is provided for protecting the clamp from short circuit connections to the transmission circuits voltage supply rails.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected respectively the head nodes and the emitters of first and second upper drive transistors. The diodes, which are preferably Schottky diodes, increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium. Additionally, a preferred embodiment of the write driver includes two voltage clamps, each coupled between a respective head node and a first supply node, to limit the magnitude of voltage spikes resulting from self-inductance of the write head.

Abstract: A first MOS transistor (5) is provided between a power source terminal and an input terminal (3). A second MOS transistor (6) is provided between a ground terminal (2) and the input terminal (3). The gate of the first MOS transistor (5) is electrically connected to a node (8) and a resistor (9) is electrically connected between the node (8) and another ground terminal (2). The gate of the second transistor (6) is electrically connected to the ground terminal (2). When negative pulse-shaped static electricity is applied to a circuit constructed as described above, the potential applied to the gate of the first MOS transistor (5) is limited low by a voltage drop developed across the resistor (9). Therefore, the current flowing between the source and drain of the first MOS transistor (5) can be controlled low and a substrate current produced due to impact ionization can be prevented from flowing. It is thus possible to obtain a stabler operation of a semiconductor integrated circuit device.

Abstract: A loading arrangement for an input stage of a source coupled logic gate comprises a loading element having at least one resistive element and at least one voltage limiting element connected in parallel with one another. There is also disclosed a loading arrangement comprising resistive and voltage limiting elements connected in parallel.

Abstract: A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A semiconductor unit is composed of an analog unit, a digital unit, a signal line through which a signal is transmitted from the analog unit to the digital unit, an electric source line Vdd1 through which a high voltage is applied to the analog unit, an electric source line Vdd2 through which the high voltage is applied to the digital unit, an electric source line Vss1 through which a low voltage is applied to the analog unit, an electric source line Vss2 through which the low voltage is applied to the digital unit, and a protective circuit arranged between the electric source lines Vss1 and Vss2. The protective circuit functions to electrically connect the electric source line Vss1 and the electric source line Vss2 in cases where an electric potential difference between the electric source lines Vss1 and Vss2 exceeds a prescribed value. Similar protection can be provided between the high voltage source lines Vdd1 and Vdd2 or between the signal line and the second source lines Vdd2 and Vss2.

Abstract: Disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; first and second diodes which are in parallel and reversely to each other connected between a back gate of the first transistor and a high-potential power source; and third and fourth diodes which are in parallel and reversely to each other connected between a back gate of the second transistor and a low-potential power source.

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.The method of this invention provides for:the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; andthe utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

Abstract: A circuit suppresses an additive transient disturbance in an input signal. A main signal path transmits the input signal, and a switchable signal path is switchable into the main signal path during a portion of the disturbance. A positive envelope detector and a negative envelope detector detects, respectively, a positive envelope signal and a negative envelope signal. In response to these signals, positive and negative envelope signals are subtracted from the main signal path only during the portion of the disturbance.

Abstract: A pre-biasing technique for a transistor-based avalanche circuit which improves the initial rate of rise in the current applied through a laser diode or other light emitting device in a laser based distance measurement and ranging instrument and, therefore, the sharpness of the leading edge of the laser pulse produced. Since the timing of the flight time of a laser pulse to a target and back to the ranging instrument is determined with reference to the leading edge of the emitted laser pulse, the inherent precision obtainable is enhanced by the production of a sharper leading edge pulse. Through the use of the pre-biasing technique disclosed, the very rapid rise time pulse which may be achieved also allows for the substitution of a much cheaper light emitting diode in lieu of a conventional laser diode in an alternative implementation of a light pulsed-based distance measuring and ranging instrument.

Abstract: An insulated gate electrical load driving device includes simple and accurate gate control circuitry for limiting load current therethrough. Preferably, all circuitry is formed of a single integrated circuit having the insulated gate load driving device dielectrically isolated from the gate control circuitry. The gate control circuitry may include either one, or both, of a zener diode and a resistor divider. An input drive signal to the circuit is accurately controlled by the gate control circuitry to thereby limit the saturation current through the insulated load driving device, and hence the load current, to predetermined current level. Preferably, the predetermined saturation current level falls within a range of saturation currents of the insulated gate load driving device that is substantially constant over a wide operating temperature range.

Abstract: An output driver that allows for static protection during generation of static discharge. The output driver includes a static protection circuit located between a predrive stage and a power drive stage.

Abstract: A device compensated for an undesired capacitance includes a first and a second node between which nodes the undesired capacitance is present. A diode driven in breakthrough is coupled between the first and the second node. As a diode driven in breakthrough exhibits the characteristics of a negative capacitance, a compensation of the undesired capacitance is achieved.

Abstract: An object of the present invention is to provide a power line connection circuit which obtains a desired turn-on resistance and a turn-off resistance without using a complex external circuit. The power line connection circuit provides a MOS transistor arranged in a power supply line, whose continuity is changed by applying a control signal from a control unit; a voltage conversion means for converting the voltage of the control signal; and a clamp means for clamping the converted voltage output from the voltage conversion means so as to have a predetermined voltage difference with respect to the voltage of said power supply line.

Abstract: The inventor has created several methods to eliminate or greatly reduce the ground loop problem. The inventor has discover that ground loop distortion is caused by the switching from positive to negative in alternating current. He has designed several devices to eliminate this problem. In his first embodiment he places a set of two diodes either cathode to cathode or anode to anode, or a neon bulb, or piezoelectric crystals in parallel with all the capacitors in an amplifier or other electronic device. These sets of diodes eliminate the ground loop distortion within the amplifier or electronic device. The applicant has also devises several power supply that eliminate or greatly reduce the ground loop distortion in an amplifier or electronic device they are attached to. Also the applicant has found that by attaching two diodes either anode to anode or cathode to cathode, or a neon bulb, or a piezoelectric crystals between an audio, video or digital cable and its ground will reduce distortion within the cable.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A sample hold circuit comprises a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal, series-connected first and second diodes having a cathode of the first diode connected to an emitter of the first transistor, a first constant current source having its one end connected to an anode of the second diode circuit and its other end connected to the voltage supply terminal, a first differential circuit including a first branch connected to the emitter of the first transistor and a second branch connected to the anode of the second diode, a third diode having its cathode connected to the anode of the second diode, a second transistor having its base connected to a connection node between the second diode and the third diode and its collector connected to the voltage supply terminal, a second differential circuit including a first branch connected to the voltage supply terminal and a second branch connected to an emitter of the second transistor,

Abstract: A semiconductor circuit which has such a configuration that a power supply terminal connected to an overvoltage protection circuit is formed independently from a power supply terminal connected to a semiconductor circuit unit, or that an overvoltage protection circuit and a semiconductor circuit unit are connected to a common power supply terminal with wirings branched from the power supply terminal with an overcurrent flowing through the overvoltage protection circuit prevented from flowing into the semiconductor circuit unit.

Abstract: A gate drive circuit which has an active voltage clamp is disclosed. The active voltage clamp protects the gate of a power transistor from an electrical over-stress condition. The active voltage clamp includes at least one zener diode connected in series with a current mirror.

Abstract: A bipolar semiconductor integrated circuit for driving a motor and the like wherein a semiconductor pattern and a circuit are so contrived that an erroneous operation will not take place even when a negative potential is applied to the output terminal of the circuit. When a negative potential is applied, there exists a quantitative proportional relationship between a parasitic current of a parasitic transistor and a ratio of the lengths of the collectors. The parasitic current decreases with a decrease in the length of the collector. Therefore, the short side of a transistor in the control circuit is directed to the output transistor to which a negative potential will be applied. By detecting the parasitic current and by adding a current to the constant-current using a current mirror circuit, furthermore, erroneous operation due to parasitism can be completely prevented.

Abstract: According to the present invention, schottky diode technology is used to limit the amount of stored charge which must be overcome by an RF transistor during the portion of an RF cycle when the RF transistor attempts to turn on. Limiting the amount of stored charge stabilizes the bias point of the RF transistor on its load line so that the mode of operation of the RF transistor may be maintained. Thus, a schottky diode is placed in a RF transistor circuit and acts as a current sink to bleed stored charge to ground. Placement of the schottky diode close to the RF transistor provides a number of benefits, including introduction of the schottky diode at a low impedance point of the RF transistor circuit, minimization of lead/lag phase angles introduced by intervening matching elements, and minimization of resonance effects.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: A semiconductor integrated circuit comprises a signal input terminal, a power supply voltage terminal to which a power voltage is applied, a reference voltage terminal to which a ground voltage is applied, a first PMOS transistor having a drain, a gate connected to the signal input terminal, and a source connected to the power supply voltage terminal, a second PMOS transistor having a gate and a drain being mutually connected to each other, and a source connected to the drain of the first transistor, a third PMOS transistor having a gate connected to the drain of the second transistor, a source connected to the power supply potential terminal, and a drain connected to the drain of the first transistor, an NMOS transistor having a gate connected to the power supply voltage terminal, a drain connected to the drain of the second PMOS transistor, and a source connected to the reference voltage terminal, an internal circuit connected to the drain of the NMOS transistor, a first overvoltage absorption element, conn

Abstract: Disclosed are a noise eliminating element having a junction of components of two kinds of electroconductive materials, characterized in that the absolute values of the thermoelectric power of the two kinds of materials is 50 .mu.VK.sup.-1 or higher and there is substantially no rectifying action at the junction. Both the Seebeck effect and the Paltier effect occur simultaneous and create a transient phenomena in one element. Because of the transient phenomena in one element and because of the transient phenomenon based on both effects, noises, particularly the standing wave noises generated at around output current near to zero are eliminated. The noise eliminating elements can be inserted in a magnetic circuit of a speaker circuit for acoustic equipment or in a deflecting coil circuit of an electron image display device.

Abstract: A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.