Using Diode Patents (Class 327/320)
  • Patent number: 9231403
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 8866529
    Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: October 21, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventors: Tse-Hung Wu, Chao-Kai Tu
  • Patent number: 8773191
    Abstract: One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu Jin Park, Han Yang, Sin-Hwan Lim, Kyo Jin Choo, Seog Heon Ham
  • Patent number: 8742819
    Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22,TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: June 3, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy B. Merkin, Susan A. Curtis, Harish Venkataraman
  • Patent number: 8704578
    Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 22, 2014
    Assignee: Rensas Electronics Corporation
    Inventor: Tatsumfi Kurokawa
  • Publication number: 20130265855
    Abstract: A switching circuit for transmission channel for ultrasound applications is electrically coupled between a connection terminal and a low voltage output terminal. The switching circuit includes a receiving switch, a high voltage clamp circuit electrically coupled between the connection terminal and a central node, and a low voltage clamping switch electrically coupled between said central node and a reference voltage. The receiving switch is a low voltage switch and is electrically coupled between the central node and the low voltage output terminal. The clamping switch and the receiving switch are controlled in a complementary way with respect to each other.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Davide Ugo Ghisu, Antonio Ricciardo, Sandro Rossi
  • Patent number: 8536924
    Abstract: Apparatus and methods for an integrated circuit, high-impedance network are provided. In an example, the network can include an anti-parallel diode pair coupled between first and second nodes. The anti-parallel diode pair can include a first diode including a P+/NWELL junction and a second diode including N+/PWELL junction. In an example, the first diode and the second diode can include a common substrate.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Andrew M. Jordan, Hrvoje Jasa, Steven M. Waldstein
  • Patent number: 8493122
    Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 23, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nidhi Chaudhry, Parul K. Sharma
  • Patent number: 8440061
    Abstract: A device for use with an RF generating source, a first electrode, a second electrode and an element. The RF generating source is operable to provide an RF signal to the first electrode and thereby create a potential between the first electrode and the second electrode. The device comprises a connecting portion and a current sink. The connecting portion is operable to electrically connect to one of the first electrode, the second electrode and an element. The current sink is in electrical connection with the connection portion and a path to ground. The current sink comprises a voltage threshold. The current sink is operable to conduct current from the connecting portion to ground when a voltage on the electrically connected one of the first electrode, the second electrode and the element is greater than the voltage threshold.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 14, 2013
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Ed Santos
  • Patent number: 8283963
    Abstract: An output stage, especially a switching output stage for switching inductive loads, having a plurality of individual output stages that are connected in parallel, which include degenerative transistors, in the degenerative path of which one respective Zener diode is present. The electric power during a switching-off process can be distributed in a particularly uniform manner to the individual output stages or transistors by disposing the Zener diodes near the associated transistors so that they are thermally coupled to the respectively associated transistor and their Zener voltage increases with increasing temperature.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 9, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Uwe Lueders, Juergen Eckhardt, Bernd Mueller
  • Patent number: 8253471
    Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 28, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Bennett, Hrvoje Jasa
  • Patent number: 8022745
    Abstract: The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: September 20, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: David C. Dening, Philippe Gorisse
  • Patent number: 7852125
    Abstract: A switching circuit arrangement includes a field effect transistor and circuitry for biasing the gate voltage of the field effect transistor, e.g., forcing the gate voltage of the field effect transistor under a certain threshold. Reverse recovery and gate bounce are simultaneously mitigated. The biasing circuitry includes a biasing diode connected in series to the gate of the field effect transistor to bias the gate voltage of the field effect transistor. A clamping field effect transistor unit is connected between the gate of the field effect transistor and the source of the field effect transistor to force the gate voltage of the field effect transistor under a certain threshold.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: December 14, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Toni Lopez, Reinhold Elferich
  • Patent number: 7760004
    Abstract: Clamp networks are provided to insure successful operation of a variety of electronic circuits that are realized in the form of integrated circuit chips. These networks are especially suited for use in chips in which on-chip circuits generate a voltage to bias the chip substrate relative to the chip ground. The clamp networks are configured to drive a current between the chip ground and the chip substrate whenever the chip substrate begins to rise above the chip ground during turn on of the chip input voltage. The clamp networks thus insure that the chip substrate is properly biased when the input voltage has been established and that the chip, therefore, functions as intended.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: July 20, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Jeffrey G. Barrow, Hio Leong Chao, Sheetal Gupta
  • Patent number: 7724061
    Abstract: An active clamp circuit for electronic components includes two sets of diode connected transistors that are inversely connected in parallel across an output of the component for providing both positive and negative differential conducting paths. The diode connected transistors cooperatively operate to limit a differential output voltage between the positive and negative conducting paths. An emitter follower buffer includes the clamp circuit and is configured to limit RF energy incident to an analog to digital converter (ADC). The emitter follower buffer includes two input transistors having their emitters each connected to at least one diode connected transistor connected to the clamp circuit. A receiver includes the differential amplifier and an analog to digital converter. A method for limiting the energy of analog signals in the receiver includes the step of operating the clamp circuit to limit the analog signals transmitted to the analog to digital converter (ADC).
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Raytheon Company
    Inventors: Won Chon, Nick J. Rosik, Harry H. Kim, Gregory D. Surbeck, Gharib Gharibianians, Dean W. Schoettler
  • Patent number: 7362157
    Abstract: A circuit arrangement is disclosed herein having an input terminal configured to receive an input voltage, and an output terminal to provide an output voltage for a load. A first transistor with a load path and a control terminal is connected between the input terminal and output terminal. A first resistance element is connected between the control terminal of the first transistor and the input terminal. A first driver circuit is connected to the control terminal of the first transistor and is configured to control a current flow through the first transistor in a forward direction. A second driver circuit is provided which is designed to detect a voltage difference between the input terminal and output terminal, and then to drive this first transistor as a function of the voltage difference in a blocking action.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: April 22, 2008
    Assignee: Infineon Technologies AG
    Inventor: Andrea Logiudice
  • Patent number: 7362141
    Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: April 22, 2008
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Yao-Chi Wang, Ying-Tang Chang, Ching-Wen Pan, Chin-Pin Yu
  • Patent number: 7279952
    Abstract: A voltage converter includes a first N-channel MOSFET transistor, an inverter, a plurality of serially-connected diodes and a second N-channel MOSFET transistor. The inverter is coupled to the gate of the first N-channel MOSFET transistor to turn on/off the voltage converter. The anode of the diodes is coupled to the source of the first N-channel MOSFET transistor and the cathode of the diodes are coupled to the drain of the second N-channel MOSFET transistor. Since the source of the second N-channel MOSFET transistor is ground, the voltage clamped at the source of the first N-channel MOSFET transistor is not higher than 3.4V when a high voltage applied to the gate of the second N-channel MOSFET transistor turns it on.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: October 9, 2007
    Assignee: Altera Corporation
    Inventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang (Bill) Liu
  • Patent number: 7239184
    Abstract: A low power and high efficiency voltage-to-current (V/I) converter designed with few parts and having improved power supply rejection. The V/I converter may include an op-amp, a MOSFET, and a first and second voltage dividers. The first voltage divider circuit may include a first, second, third, and fourth resistors. A source terminal of the MOSFET may be connected to a junction of the third and fourth resistors and the fourth resistor may be connected to a positive supply rail. Also, an inverting input terminal of the op-amp may be coupled to a junction of the second and third resistors. Additionally, the second resistor may be coupled to the first resistor, which may be connected to an input terminal of the V/I converter. The V/I converter typically has very good DC rejection of the power supply because the first and second voltage dividers are designed to have the same ratios.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: July 3, 2007
    Assignee: National Instruments Corporation
    Inventors: Raffaele Cetrulo, Mark Whittington
  • Patent number: 6947337
    Abstract: Random-access memory device having select lines, bit lines, and several RAM cells, each RAM cell being connected to a corresponding one of said select lines and to a corresponding one of said bit lines. The random-access memory device further having select buffers for selecting the read-out of one out of the selected lines when receiving a selection signal. Each of the select buffers having an inverter serving as driver. The inverter is being followed by a diode for limiting output voltage swings at the respective select line.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 20, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Nikola Stojanov
  • Patent number: 6879203
    Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: April 12, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Yi-Hsu Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 6853232
    Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Rainald Sander, Frank Kahlmann, Veli Kartal, Detlef Kalz, Helmut Hertrich
  • Patent number: 6777996
    Abstract: A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cathode connected to the input/output node (12); a third diode (D3) connected between the cathode of the first diode (D1) at a first node (14) and the anode of the second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode of the first diode at first node (14); a second arrangement for supplying a second potential at the anode of the second diode at second node (16); a first capacitor (C1) connected between the cathode of the first diode at first node (14) and ground; and a second capacitor connected between the anode of the second diode at second node (16) and ground.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: August 17, 2004
    Assignee: Raytheon Company
    Inventor: Marlin C. Smith, Jr.
  • Patent number: 6714061
    Abstract: A circuit for reducing leakage current in an ESD overvoltage protection circuit is described. Specifically, the circuit uses a semiconductor controlled rectifier or a semiconductor controlled switch to minimize the leakage.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: March 30, 2004
    Assignee: Intel Corporation
    Inventor: Scott Hareland
  • Patent number: 6700428
    Abstract: A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first drive input for applying a first drive signal, and a first semiconductor switching element having a first load terminal connected to the first connecting terminal, a second load terminal connected to the second connecting terminal and a drive terminal coupled to the drive input. A voltage limiting circuit is provided and is connected between the first load terminal and the drive terminal of the first semiconductor switching element.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: March 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Rainald Sander
  • Publication number: 20030189453
    Abstract: A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cathode connected to the input/output node (12); a third diode (D3) connected between the cathode of the first diode (D1) at a first node (14) and the anode of the second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode of the first diode at first node (14); a second arrangement for supplying a second potential at the anode of the second diode at second node (16); a first capacitor (C1) connected between the cathode of the first diode at first node (14) and ground; and a second capacitor connected between the anode of the second diode at second node (16) and ground.
    Type: Application
    Filed: March 11, 2003
    Publication date: October 9, 2003
    Inventor: Marlin C. Smith
  • Patent number: 6590435
    Abstract: A method and apparatus that restrict the differential output voltage (VOD) for an LVDS input buffer is provided. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. Clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. When a clamping circuit is active, an alternate current path is provided maintaining the level of the signal before clamping.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: July 8, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Douglas M. Hannan, David J. Haas
  • Patent number: 6531908
    Abstract: A power output stage for switching inductive loads contains a series circuit having a load and a switching transistor. A series connected circuit formed of a blocking diode and a multiplicity of Zener diodes is disposed between the drain and gate electrodes of the switching transistor. A capacitor, a resistor or a series or parallel circuit of a capacitor and a resistor is disposed in parallel with at least one of the Zener diodes. The circuit configuration rounds off the pronounced kink in the drain voltage when the Zener protection cuts in during a switched state of the switching transistor.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 11, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerhard Goeser, Mark Elliott, Donald Preslar
  • Patent number: 6483365
    Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: November 19, 2002
    Assignee: NEC Corporation
    Inventor: Yasuyuki Morishita
  • Patent number: 6472923
    Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: October 29, 2002
    Assignee: NEC Corporation
    Inventor: Yasuyuki Morishita
  • Patent number: 6437627
    Abstract: A high voltage level shifter utilizing only low voltage PMOS and low voltage NMOS devices. The high voltage level shifter is used to distribute the high voltage almost equally among the PMOS devices and almost equally among the NMOS devices to meet the device electrical specification of low voltage MOS devices for various breakdown mechanisms. A layout technique is also used to achieve a much higher junction breakdown of N+ drain to P-substrate and a better gated diode breakdown of NMOS devices.
    Type: Grant
    Filed: August 25, 1995
    Date of Patent: August 20, 2002
    Assignee: Winbond Electronics Corporation
    Inventors: Hieu Van Tran, Trevor Blyth
  • Patent number: 6426665
    Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventor: Yasuyuki Morishita
  • Patent number: 6404261
    Abstract: A switch circuit for battery-powered equipment, for example a mobile telephone or a portable computer, comprises a 4-terminal bi-directional semiconductor switch (M1) and a protection diode (Dbg). The switch (M1) has a control-gate terminal (g) for applying a control signal (Vg) to form a conduction channel (12) in a body region (11) of the switch, for turning the switch (M1) on and off between a battery (B) and a power line (2) of the equipment. The switch (M1) also has a back-gate terminal (b; bg) in a bias path that serves for applying a bias potential (Vmin) to the body region (11). The protection diode (Dbg) has a diode path in series with the back-gate terminal (b; bg) so as to provide in the bias path a rectifying barrier (25; 25′) that blocks current flow between the body region (11) and the gate-bias terminal (b, bg) in the event of a reverse voltage polarity across the switch (M1), for example when recharging the battery (B).
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: June 11, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond J. Grover, Franciscus ACM Schoofs, Pieter G. Blanken
  • Patent number: 6377120
    Abstract: A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: April 23, 2002
    Assignee: Pixart Imaging Inc.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 6351171
    Abstract: A method and apparatus for accelerating the transmission of signals across an interconnect wire of an integrated circuit is presented. According to the method, a minimum charge level is maintained on the wire when it is driven to a low voltage level and a maximum charge level is maintained on the wire when it is driven to a high voltage level. In accordance with the apparatus of the invention, the minimum and maximum charge levels are maintained on the wire using a pair of clamping circuits which clamp the voltage level on the receiving end of the wire to a respective minimum voltage level and maximum voltage level. Accordingly, when the interconnect wire is driven to a high voltage level at a driven end of the wire, the charge level on the receiving end of the wire is already at a minimum level, resulting in less delay time to charge the wire to a high voltage level.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: February 26, 2002
    Assignee: Agilent Technologies, Inc.
    Inventor: David D. Balhiser
  • Patent number: 6304126
    Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: October 16, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Denis Berthiot
  • Patent number: 6275089
    Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: August 14, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jun Song, Ting Cheong Ang, Shyue Fong Quek, Lap Chan
  • Patent number: 6271706
    Abstract: The present invention provides an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a central node. The de-coupling circuit further includes a PMOSFET transistor and a NMOSFET transistor that have their gates coupled at the node. The PMOSFET and NMOSFET transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 7, 2001
    Assignee: Intel Corporation
    Inventor: Raj Nair
  • Patent number: 6259297
    Abstract: A protection circuit is disclosed for a bipolar power transistor for preventing the operating point thereof from leaving a useful operating area. The protection circuit includes a sense resistor connected between an input supply voltage and a collector of the bipolar power transistor; a first branch circuit, including a first diode connected to the collector of the bipolar power transistor and a first current source connected between a common output node and the first diode; a second branch circuit, including a second diode and a second current source connected between the second diode and the common output node; and a third branch circuit. A short-circuit current level of the bipolar power transistor at relatively low voltage levels of the input supply voltage is based upon current levels for the first current source and the second current source and a resistance value of the sense resistor connected to the bipolar power transistor.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: July 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giovanni Galli
  • Patent number: 6222412
    Abstract: The present invention relates to a circuit for controlling waveform distortion resulting from nonlinearity of the impedance of a control terminal (gate or base) capacitance of a transistor, which can be employed in circuits showing a nonlinearity performance of high frequency amplifier or oscillator. According to the circuit of the invention, the waveform distortion can be properly controlled to improve the efficiency of power conversion in a high frequency circuit employing FET, regardless of the frequency band, while assuring a favorable matching of input for the circuit. Also, it can provide the reliability of an integrated circuit by employing outside voltage control circuit. Moreover, it can be fabricated on a wafer substrate of FET circuit with an inexpensive cost, which affords unrestricted designing of the circuit.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: April 24, 2001
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kye-Ik Jeon, Jae-Myoung Baek, Dong-Wook Kim, Song-Cheol Hong
  • Patent number: 6218882
    Abstract: A diode circuit of the present invention comprise an input/output terminal connected to the transmission line, a power supply terminal connected to the power supply, a plurality of diodes connected in series between the input/output terminal and the power supply terminal and a capacitive element having one end connected to a connected point of the plurality of diodes and the other end connected to the ground. In the input/output terminal, an applied signal from the transmission line exceeds the predetermined potential, it is clamped to the predetermined potential by the plurality of diodes connected in series. At the connecting points among a plurality of diodes and the input/output terminal, vibration of potential is reduced by the capacitance element.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: April 17, 2001
    Assignee: NEC Corporation
    Inventor: Hiroshi Kamiya
  • Patent number: 6208191
    Abstract: An improved voltage clamp for operating with wireless communication input circuits over the RF band. The clamp provides for symmetrical clamping for excessive positive and negative input voltage excursions. The clamp does not exact a current penalty when operating in the non-excessive positive and negative input voltage regimes. The clamp is comprised of an input node, a capacitor, a MOS transistor, a diode and a ground potential node.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: March 27, 2001
    Assignee: Microchip Technology Incorporated
    Inventor: Sam E. Alexander
  • Patent number: 6204717
    Abstract: A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby prevent the occurrence of the electromagnetic noise and the excessively large voltage.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Nagasu, Hideo Kobayashi, Hideki Miyazaki, Shin Kimura, Junichi Sakano, Mutsuhiro Mori
  • Patent number: 6081152
    Abstract: An output buffer interfaces a digital system having devices designed for low operating voltages to an output coupled to an external system having higher operating voltages. The output buffer drives the output to one of a high output voltage and a low output voltage while limiting voltage across terminals of devices within the output buffer. The output buffer includes a pull-up stack of a first plurality of devices, coupled between a high power supply and the output, which turn on when the output is driven to the high output voltage and which turn off when the output is driven to the low output voltage. The voltage difference between the output and the high power supply is distributed across the first plurality of devices when the output is driven to the low output voltage.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: June 27, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Reading Maley
  • Patent number: 6078204
    Abstract: An external FET (12) has protection provided thereto for excessive voltages between the gate and drain and between the gate and source. A drain-to-gate clamp is provided with a plurality of series connected zener diodes (34), (36) and (38) which are connected in series with a Schottky diode (42). The current therethrough is sensed with a resistor (56) which turns on a bypass transistor (58) to shunt current around the zener diodes when an excess voltage causes them to break down. This will turn on the FET (12). The gate-to-source clamp is configured with two zener diodes (74) and (76) which are reversed biased. A series current sense resistor (82) senses the current through the diodes and turns on a transistor (84) when the current exceeds a predetermined level. This will effectively shunt current around the zener diodes (74) and (76).
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Chris Cooper, Katherine Frank, David Baldwin
  • Patent number: 6078206
    Abstract: A small amplitude signal output circuit comprises an output section, for receiving a logic signal to output a small amplitude signal, having first and second transistors connected in series between a first source line and a second source line, and voltage control sections connected between each of the source lines and the output section for reducing the output voltage supplied from the output node, thereby allowing ON-resistance of the transistors of the output section to be smaller. The small ON-resistance of the transistors in turn allows variations in the output voltage of the output circuit caused by variations in the fabrication process to be smaller. The voltage control sections may have a function for reducing variations in the output circuit due to temperature variation.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventor: Seiichi Watarai
  • Patent number: 6066974
    Abstract: A transistor switch comprises a first field-effect transistor, a second field-effect transistor, a clamping circuit and a coupling circuit. The first field-effect transistor is controlled by a first voltage source to be turned on during a transmission mode. The second field-effect transistor, which is controlled by a second voltage source to be turned off during the transmission mode, has one current carrying terminal connected to the first field-effect transistor. The clamping circuit is connected between a gate of the second field-effect transistor and the second voltage source. The coupling circuit is connected between the gate and one current carrying terminal of the second field-effect transistor.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: May 23, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Hui Lin, Chien-Kuang Lee
  • Patent number: 6060938
    Abstract: An output buffer for reducing the signal noise associated with the switching between logic high and logic low electrical. Signals includes a first clamping circuit linked to the pull-up output transistor of the buffer, and a second clamping circuit linked to the pull-down output transistor of the buffer. The buffer may include both clamping circuits or either the first or second clamping circuit alone, dependent upon signal shaping interests. Each of the clamping circuits includes a selectable delay stage coupled to the buffer's input, a current regulator controlled by the delay stage, and a clamping device that is coupled to the control node of the output transistor. When the current regulator is conducting, the control node of the output transistor is clamped at a potential near its threshold turn-on. As a result, when the clamping circuit is turned off, the output transistor experiences a soft turn-on, thereby reducing signal bounce and the associated noise.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: May 9, 2000
    Assignee: Fairchild Semiconductor Corp.
    Inventor: David P. Morrill
  • Patent number: 6054888
    Abstract: A level shifter interfaces a digital system having devices designed for low operating voltages to an external system having higher operating voltages. The level shifter is comprised of two level shifting stages. Each level shifting stage includes a pull-up stack of a plurality of pull-up devices, coupled between a high power supply and a coupling node, which turn on when the coupling node is driven to a high shifted voltage, which is substantially the voltage at the high power supply, and which turn off when the coupling node is driven to a low shifted voltage, which is substantially the voltage at a low power supply. Each level shifting stage further includes a pull-down stack of a plurality of pull-down devices, coupled between the low power supply and the coupling node, which turn on when the coupling node is driven to the low shifted voltage and which turn off when the coupling node is driven to the high shifted voltage.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: April 25, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Reading Maley
  • Patent number: 5942931
    Abstract: A first MOS transistor (5) is provided between a power source terminal and an input terminal (3). A second MOS transistor (6) is provided between a ground terminal (2) and the input terminal (3). The gate of the first MOS transistor (5) is electrically connected to a node (8) and a resistor (9) is electrically connected between the node (8) and another ground terminal (2). The gate of the second transistor (6) is electrically connected to the ground terminal (2). When negative pulse-shaped static electricity is applied to a circuit constructed as described above, the potential applied to the gate of the first MOS transistor (5) is limited low by a voltage drop developed across the resistor (9). Therefore, the current flowing between the source and drain of the first MOS transistor (5) can be controlled low and a substrate current produced due to impact ionization can be prevented from flowing. It is thus possible to obtain a stabler operation of a semiconductor integrated circuit device.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: August 24, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tetsuro Yanai