Abstract: A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

Abstract: An overvoltage protection circuit includes an input terminal, an output terminal, a clamp transistor, and a selector circuit. The clamp transistor is configured to control current flow between the input terminal and the output terminal. The clamp transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal. The selector circuit is configured to control a resistance of the clamp transistor based on a voltage at the input terminal. The selector circuit includes a first terminal coupled to the first terminal of the clamp transistor, a second terminal coupled to the second terminal of the clamp transistor, and a third terminal coupled to a third terminal of the clamp transistor.

Abstract: A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor.

Abstract: Systems and methods for multi-threshold sensing at an audio receiver, and systems and methods for calibrating an audio system to optimize for the specific configuration of the audio system are disclosed herein. In some implementations of a multi-threshold receiver, at least one additional voltage level is selected to trigger latching events within the receiver based on changes of the receiver input (which includes differential signals Vp and Vn) and in turn, to generate internal signals within the multi-threshold receiver, and then logic operations are performed on these internal signals to generate the output of the multi-threshold receiver.

Abstract: A driver device includes a T-coil circuit and driver circuitries. The driver circuitries are averagely configured as a first driver set and a second driver set. The driver circuitries of the first driver set amplify one of a first data signal and a second data signal according to first portion of bits of an equalization signal, to generate a first output signal and to transmit the same to a first node of the T-coil circuit. The driver circuitries of the second driver set amplify one of the first data signal and the second data signal according to second portion of bits of the equalization signal, to generate a second output signal and to transmit the same to a second node of the T-coil circuit. The T-coil circuit further combines the first and second output signals as a third data signal, and transmits the third data signal to a channel.

Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Abstract: A detection circuit, provided in a gamma buffer circuit that includes at least one transistor that receives the application of a first voltage and generates gradation voltages on the basis of a plurality of gamma voltages, includes: a first comparison circuit that compares the largest gamma voltage with a substrate potential of the transistor and outputs a first comparison result signal, a second comparison circuit that includes an inverter which is operable under a second voltage as a source voltage, compares a threshold voltage of the inverter with the substrate potential, and outputs a second comparison result signal; and a detection result output circuit for outputting a detection result showing if the voltage decrease or power discontinuity of the first voltage is occurring on the basis of the first comparison result signal and the second comparison result signal.

Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.

Abstract: The invention relates to a simulation circuit of an alternating electric grid, the circuit having at least one alternating port, a bank of first resistances that can be selectively connected to the alternating port by connecting means. According to the invention, the circuit comprises a reversible AC-DC converter comprising an alternating side connected to the alternating port and a direct side connected to a sub-circuit for dissipating energy into direct current connected to an electric battery able to be charged with direct current and discharged with direct current.

Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.

Abstract: A CML latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage.

Abstract: A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.

Abstract: A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Abstract: An I/O device comprises a driving unit coupled between a first voltage and a second voltage, and configured to receive a first signal so as to drive a second signal for swing with a second swing range narrower than a first swing range between the first voltage and the second voltage and supply the second signal to a transmission line. The driving unit includes a first stabilizer coupled between the first voltage and the transmission line and a second stabilizer coupled between the second voltage and the transmission line.

Abstract: A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.

Abstract: The present disclosure includes systems and methods for sharing bias current. In one embodiment, shared bias current passes through a first level device to one or more second level devices along a bias current path. Multiple active devices may share bias current along a bias current path and process signal along the same or different signal paths. In one embodiment, bias current from one device is split among multiple devices. In another embodiment, bias current is combined from multiple devices into a device. Embodiments may include an interstage circuit along a signal path that improves stability of the circuit.

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract: A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train.

Abstract: Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.

Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Abstract: Apparatus and methods for an integrated circuit, high-impedance network are provided. In an example, the network can include an anti-parallel diode pair coupled between first and second nodes. The anti-parallel diode pair can include a first diode including a P+/NWELL junction and a second diode including N+/PWELL junction. In an example, the first diode and the second diode can include a common substrate.

Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract: The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential.

Abstract: An output stage, especially a switching output stage for switching inductive loads, having a plurality of individual output stages that are connected in parallel, which include degenerative transistors, in the degenerative path of which one respective Zener diode is present. The electric power during a switching-off process can be distributed in a particularly uniform manner to the individual output stages or transistors by disposing the Zener diodes near the associated transistors so that they are thermally coupled to the respectively associated transistor and their Zener voltage increases with increasing temperature.

Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.

Abstract: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide band-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

Abstract: A driver circuit includes an output section; a voltage-dividing section configured to divide a first voltage at a coupling point between the output section and a termination resistor; a comparison section configured to compare a voltage difference with one of the first voltage and a second voltage, the voltage difference being a difference between the second voltage at a coupling point between the termination resistor and a transmission path and a third voltage output from the voltage-dividing section; and an adjustment section configured to adjust a voltage division ratio of the voltage-dividing section on the basis of the comparison result obtained in the comparison section.

Abstract: A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being connected to a far end of the signal line, receiving a second signal at the near end of the signal line from the remote device and deriving a second digital data stream therefrom, having a replica generator for providing, in response to the first digital data stream or a signal derived therefrom, a replica signal, and an extraction circuit for extracting the second digital data stream from the second signal in response to the replica signal and a comparator signal deduced from the near end of the signal line and an automatic test equipment having a plurality of communication circuits each providing a bi-directional data transmission.

Abstract: A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

Abstract: The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.

Abstract: A method to clamp an open circuit voltage in a photovoltaic module is proposed. The method include coupling a load resistor across an inverter module, initiating the inverter module and loading the inverter module via the load resistor, and coupling the loaded inverter module to the photovoltaic module. The method further include dissipating power via the load resistor to clamp the open circuit voltage of the photovoltaic module, synchronizing an output voltage of the inverter module with a voltage of a grid and then coupling the inverter module to the grid and de-coupling the load resistor across the inverter module.

Abstract: A switching circuit arrangement includes a field effect transistor and circuitry for biasing the gate voltage of the field effect transistor, e.g., forcing the gate voltage of the field effect transistor under a certain threshold. Reverse recovery and gate bounce are simultaneously mitigated. The biasing circuitry includes a biasing diode connected in series to the gate of the field effect transistor to bias the gate voltage of the field effect transistor. A clamping field effect transistor unit is connected between the gate of the field effect transistor and the source of the field effect transistor to force the gate voltage of the field effect transistor under a certain threshold.

Abstract: When an insulated gate bipolar transistor turned on starts to transition to turn off, the insulated gate bipolar transistor has between the emitter and the collector a surge voltage caused in proportion to the magnitude of a current gradient provided when a current flowing through a coil in switching is interrupted and an electrode interconnect inductance internal to an inverter circuit. A MOS transistor is temporarily turned on within a period of time for which the insulated gate bipolar transistor turned on transitions to turn off. This can bypass a portion of the current to the MOS transistor. This can provide an alleviated apparent current gradient of the current and thus alleviate or prevent a surge voltage caused at the insulated gate bipolar transistor.

Abstract: A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, whilst the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost.

Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.

Abstract: An active matrix display device has column address circuitry for generating pixel drive signals. The column address circuitry has an output buffer for providing a pixel drive signal to a column conductor, and the positive and negative slew rates of the output buffer are different. By selecting the positive and negative slew rates independently in the design of the output buffer, the size of the transistors (54, 56), particularly those which pass the charging (or discharging) current of the column capacitance, can be kept to a minimum.

Abstract: A circuit arrangement is disclosed herein having an input terminal configured to receive an input voltage, and an output terminal to provide an output voltage for a load. A first transistor with a load path and a control terminal is connected between the input terminal and output terminal. A first resistance element is connected between the control terminal of the first transistor and the input terminal. A first driver circuit is connected to the control terminal of the first transistor and is configured to control a current flow through the first transistor in a forward direction. A second driver circuit is provided which is designed to detect a voltage difference between the input terminal and output terminal, and then to drive this first transistor as a function of the voltage difference in a blocking action.

Abstract: In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Abstract: A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complementary logic signal with respect to the first input node, the first and second input nodes associated with the lower operating voltage. A first pull up device is in series with the first pull down device and second pull up device is in series with the second pull down device, with the first and second pull up devices coupled to a power supply at the higher operating voltage. An output node is between the second pull down device and the second pull up device, the output node controlling the conductivity of the first pull up device. A clamping device is in parallel with the first pull up device, and configured to prevent the second pull up device from becoming fully saturated.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: Circuit comprising a signal input (11) for receiving an input signal (s(t)) and a digital output stage (15) being designed for operation at a supply voltage (VDD). The output stage (15) comprises a series of two n-channel CMOS transistors (no1, no2), a common node (17) between the two n-channel CMOS transistors (no1, no2), and an output port (16). Active voltage limiting means (14) are arranged between the signal input (11) and the common node (17) for limiting voltages (VNM) at the common node (17) to a voltage limit (Vmax). The voltage limiting means (14) are controllable byte state of the input signal (s(t)).

Abstract: An integrated circuit (IC) uses a current source coupled to means for current-to-voltage conversion to reject the unwanted high voltage signal and detects the wanted small voltage signal. In particular, the current source produces mirrored currents proportional to the high voltage signal, while the means for converting current-to-voltage rejects the common-mode current when there is no small signal voltage flowing through the sensing resistor. On the other hand, when the small signal voltage exists, a current flows across the sensing resistor and disturbs the balance of the current mirror. As a result, the common mode no longer exists and the means for converting current-to-voltage converts and amplifies this small signal current into a voltage proportional to the small voltage signal.

Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.

Abstract: An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a transition signal in response to a detection of a transition from a first state to a second state on the interconnect line and further generates the transition signal in response to a detection of a transition from the second state to the first state on said interconnect line. The receiver further includes an output signal control circuit that, in response to the transition signal, selectively outputs either a present state of said interconnect line or a next state of the interconnect line stored in the receiver.

Abstract: An input buffer comprises: a pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting a signal applied to the input pad; a buffer generating an input signal by buffering the signal applied to the transmission transistor; and a control circuit generating a voltage applied to the input pad as the control voltage and the floating well voltage when a high voltage is applied to the input pad, generating the ground voltage as the control voltage and the power supply voltage as the floating well voltage in the case where a voltage less than the high voltage is applied to the input pad.

Abstract: A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

Abstract: The present invention provides a Driver circuit having dynamically adjusting output current and limiting input current function. This present invention dynamically adjusts the output current provided by the driver unit to reduce this output current in real time. A protection circuit is also provided to limit the input current supplied to the driver unit. This present invention avoids overdriving the driver unit.

Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.