Abstract: A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.

Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.

Abstract: Various embodiments may provide a comparator circuit arrangement. The comparator circuit arrangement may include a preamplifier having a first input configured to be coupled to a first input voltage, a second input configured to be coupled to a second input voltage, and an output configured to generate a preamplifier output signal based on the first input voltage and the second input voltage. The comparator circuit arrangement may also include a switch circuit arrangement coupled to the preamplifier, the switch circuit arrangement configured to deactivate the preamplifier upon the second input voltage exceeding the first input voltage and further configured to activate the preamplifier upon a fall of the second input voltage, and a pull-up circuit arrangement coupled to the output of the preamplifier, the pull-up circuit arrangement configured to provide a boost voltage to the preamplifier output signal for a predetermined duration upon the fall of the second input voltage.

Abstract: In one aspect, a gate driver circuit includes a clamp circuit connecting a first node to a second node. The clamp circuit is configured to provide a clamp voltage. The gate driver circuit also includes a first driver connected to the first node and to the second node. The first driver comprising a first input configured to receive the clamp voltage from the clamp circuit. The gate driver circuit further includes a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.

Abstract: According to an aspect, an overvoltage protection circuit includes a bias current generator configured to generate a bias current, and a current comparator configured to receive the bias current and a voltage associated with a data terminal of a connector. The current comparator includes a transistor. The transistor is configured to activate based on a level of the voltage associated with the data terminal. The current comparator is configured to compare a current of the transistor with the bias current. The overvoltage protection circuit includes an output circuit configured to generate an overvoltage protection signal in response to the current of the transistor being greater than the bias current.

Abstract: An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element.

Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.

Abstract: A cable connector assembly including: a first electrical connector comprising a frontal first mating member for inputting a first voltage, a first voltage point for outputting the first voltage, and a second voltage point for outputting a second voltage different from the first voltage; a second electrical connector comprising a frontal second mating member and a second printed circuit board, the second mating member comprising a power contact; and a cable connecting the first electrical connector and the second electrical connector electrically, the cable comprising a first wire and a second wire, the first wire connecting the first voltage point and the power contact electrically, the second wire connecting the second voltage point and the second printed circuit board electrically.

Abstract: A level shifter that includes: a power supply system current source; a second transistor having a third main electrode that is connected to an input voltage signal terminal, a fourth main electrode that is connected to an output voltage signal terminal, and a second control electrode that is connected to a third power supply voltage having a voltage that is lower than a first power supply voltage and higher than a second power supply voltage; a second resistor; and a third transistor having a fifth main electrode that is connected to the second end of the second resistor, a sixth main electrode that is connected to the second power supply voltage, and a third control electrode that is connected to a first control electrode of a first transistor of the power supply system current source.

Abstract: An integrated circuit is provided with a voltage sag detector (VSD) within the integrated circuit package. The VSD is coupled to a voltage reference and to the power distribution bus within the integrated circuit. The VSD has an output for indicating when a voltage level on the power distribution bus sags below a voltage level provided by the voltage reference.

Abstract: The present disclosure relates to a control circuit of the switching power supply including a soft-booting voltage generation circuit, a first comparator, a voltage selection circuit, a switching circuit, a second comparator, an error amplification circuit, and a pulse signal control circuit. During the soft-booting phase and during the operational phase, different superposition voltages are superposed with the control voltage by the voltage selection circuit to obtain the clamping voltage. Thus, different clamping voltages are configured during the soft-booting phase and the operational phase, which contributes to the system stability. In addition, when the output voltage of the switching circuit is greater than the reference voltage, the second comparator outputs the first high level signals to the clock signal generator. The clock signal generator then stops operations, that is, and the control circuit of the switching power supply is in the sleep mode, which enhances the efficiency of the power.

Abstract: Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

Abstract: Systems and methods for providing automatic short circuit protection in an electrical system via a switching device. In some embodiments, the switching device includes a switching transistor that selectively switches between an open position and a closed position based at least in part on a switching control signal, for example, to facilitate converting electrical power with first electrical characteristics output into electrical power with the second electrical characteristics.

Abstract: Damages to the rectifying MOSFET in the secondary side of voltage converters are reduced or eliminated by inserting intermediary steps between detecting a dropping in the converter output voltage VCC and activating the under voltage lock out (UVLO) circuitry. During the intermediary steps, the timing for switching off the MOSFET is advanced to prevent the current flow in the MOSFET from reversing its direction.

Abstract: A cyber-security system, including a device and associated method, provides secure communications bi-directionally between an external network and an internal network, including a supervisor control and data acquisition (SCADA) device. The device includes a processor in data communication with the external and internal networks that is programmed with a rule-set establishing validation criteria configured to validate data received from the external and internal networks. The processor is operable in an operational mode to pass between the external and internal networks only data that are compliant with the validation criteria. The processor may be configured to save certain validated data indicating a system state that can inform the application of the rule-set to data. The processor is re-programmable with a new rule-set only in a programming mode. The device includes a switch that is manually operable to switch the processor from the operational mode to the programming mode.

Abstract: A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.

Abstract: A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.

Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.

Abstract: The invention relates to an electronic device comprising an RF-LDMOS transistor (1) and a protection circuit (2) for the RF-LDMOS transistor. The protection circuit (2) comprises: i) an input terminal (Ni) coupled to a drain terminal (Drn) of the RF-LDMOS transistor (1); ii) a clipping node (Nc); iii) a clipping circuit (3) coupled to the clipping node (Nc) for substantially keeping the voltage on the clipping node (Nc) below a predefined reference voltage, wherein the predefined reference voltage is designed to be larger than the operation voltage on the drain terminal (Drn) and lower than a trigger voltage of a parasitic bipolar transistor (100) that is inherently present in the RF-LDMOS transistor; iv) a capacitance (Ct) coupled between the clipping node (Nc) and a further reference voltage terminal (Gnd), and v) a rectifying element (D1, D2) connected with its anode terminal to the input terminal (Ni) and with its cathode terminal to the clipping node (Nc).

Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.

Abstract: A voltage clamp circuit includes a power supply, a first element connected with the power supply to output a constant current, a third element configured to allow a current to pass through when a voltage of a predetermined value or more is applied; and a second element configured to output a voltage according to a voltage generated by the first and third elements.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages, and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.

Abstract: A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.

Abstract: A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. The power line carrier communication reception circuit may include an amplifier which is connected to a power line and amplifies a received signal to be superimposed on the power line; two capacitors which are connected in series between both power sources of the amplifier; and a clipper circuit which connects connection points of these capacitors to the power line and limits the received signal in a predetermined range of a reference voltage between the capacitors, and in which the amplifier compares the signal limited by the clipper circuit and the reference voltage and amplifies the signal.

Abstract: According to an embodiment, an FET drive circuit includes an FET, a first circuit, a resistor and a third rectifying device. The first circuit includes a first rectifying device, a second rectifying device and a capacitive element sequentially provided in series from a drain to a gate of the FET, the first rectifying device allowing a forward electric current flowing from the drain to the gate, and the second rectifying device having a predetermined breakdown voltage with respect to the electric current from the drain to the gate. The resistor is provided between a power source and a connecting point of the second rectifying device and the capacitive element; and the third rectifying device provided between a source and a gate of the FET.

Abstract: In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed.

Abstract: An integrated circuit includes a high voltage transistor having a first terminal coupled to sense a high voltage terminal and a control terminal coupled to a regulated voltage, which is regulated with respect to a ground terminal and is substantially less than a high voltage that the high voltage terminal is adapted to withstand. A logic gate is also included and is coupled to be powered from the regulated voltage. The logic gate has an input threshold that is less than the regulated voltage. An input terminal of the logic gate is coupled to a second terminal of the high voltage transistor. An output of the logic gate is coupled to indicate that a voltage sensed between the high voltage terminal and the ground terminal is less than the input threshold voltage of the logic gate.

Abstract: Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.

Abstract: This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: A clamp-point active circuit is provided. The clamp-point active circuit includes a rate amplifier configured to receive an output from a device transitioning between at least two levels. The clamp-point active circuit has at least one switching device configured to receive an output from the rate amplifier. The at least one switching device is in at least one respective feedback loop of the rate amplifier. A switching of the at least one switching device causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to a fixed level.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: An output circuit includes a first transistor coupled to an external terminal and having a gate terminal that receives a first drive signal. The first transistor pulls down a potential at the external terminal when activated in accordance with the first drive signal. The output circuit also includes a capacitor. The capacitor includes a first end coupled to the gate terminal of the first transistor. A clamp circuit, coupled to a second end of the capacitor, clamps the second end of the capacitor to a potential corresponding to the operation of the first transistor. The first transistor includes a drain terminal that is not coupled to the capacitor but is coupled to the external terminal.

Abstract: A voltage-limiting circuit, including a series branch circuit having a plurality of power switching devices, a plurality of energy temporary-storage circuits, and a centralized voltage-limiting circuit for limiting voltage for the series branch circuit. Each power switching device includes a control terminal, a high-end, and a low-end, and is connected in parallel with one energy temporary-storage circuit. The energy temporary-storage circuits include clamping diodes, energy storage capacitors, static voltage-sharing resistors, and energy return ends. In each energy temporary-storage circuit, the energy storage capacitors are connected in parallel with the static voltage-sharing resistors to form the energy return ends, and then connected in series with the clamping diodes. The centralized voltage-limiting circuit includes a voltage-limiting functional circuit and a plurality of energy concentration diodes for concentrating the energy temporarily stored by the corresponding energy temporary-storage circuits.

Abstract: A snubber circuit for a chopper circuit has at least one chopper transistor with terminals connected to a first line and to a second line, the first line being at a power supply potential and the second line being at ground potential. The snubber circuit has a capacitive element and a charging diode for charging the capacitive element. The charging diode and the capacitive element are connected in series to each other and together they are connected in parallel with the chopper transistor. The snubber circuit has an inductive element having a first end connected to a connection point situated between the charging diode and the capacitive element, and a second end connected to one of the lines.

Abstract: An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.

Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.

Abstract: A circuit arrangement in which a further electronic component for connecting and amplifying an electrical voltage is arranged between a first series arm and a second series arm to achieve limiting of a voltage between a first clamping point and a second clamping point in the circuit arrangement. An input of the second component is connected by a resistor to the output of a third component, and a device for producing a second reference voltage is arranged between the second series arm and the second component such that it is possible lower the voltage at the first clamping point when the flow of current through the load resistor is interrupted.

Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.

Abstract: Conventional circuits often have undesirable characteristics to due “hot spots” or use a large amount of area. Here, however, a charging circuit is provides that uses an improved driver. Namely, an amplifier within a current sensor is used to control the rate that a switch can charge an external capacitor. This is accomplished through the adjustment of the gain of the amplifier during a charging mode.

Abstract: An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

Abstract: The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.

Abstract: A low side clamp circuit has a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. The control portion and sense portion have cross-coupled transistors that create increased speed and a sharp response with little or no voltage offset with a wide range of load currents. A clamp current source draws current through a resistor coupled in series between the base of the output transistor in the control portion and the collector of the output transistor in the sense portion. The clamp current is set to ClLo/R, where ClLo is the clamp voltage. A high side clamp is also described.

Abstract: Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node of the device and includes circuitry that is configured to compare the supply voltage node and the output node. In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches are used to place the device in different modes in response to the output signal.