Abstract: An input circuit which prevents erroneous operation caused by noise. An input stage has a NMOS transistor N11 and a PMOS transistor P11. A NMOS transistor N12 is connected in series between a ground line and the source of the NMOS transistor N11. A PMOS transistor P12 coupled to a voltage supply line V.sub.cc acts as a current control element. NMOS transistors N13 and N14 are connected in series between the ground line and the drain of PMOS transistor P12. Inverters IV11 and IV12 delay the voltage of an intermediate output node S11 and supply it to the gate of NMOS transistor N13. The gate of NMOS transistor N12 is coupled to a node S13, the gate of NMOS transistor N14 is coupled to the input line for an input signal IN, and node S13 is formed to function as a voltage sensor with respect to the ground.

Abstract: A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus.

Abstract: An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.

Abstract: A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors.

Abstract: The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external components. The microcontroller can function in a proper manner from the application of only power and signal lines with no external components required. The microcontroller has integrated internal reset and oscillator circuitry into the microcontroller. The microcontroller has also integrated simple external components such as current limiting resistors and pull u and pull down resistor into the microcontroller in order to avoid application specific external components.

Abstract: A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.

Abstract: There is provided a semiconductor integrated circuit including an output circuit having a first buffer section to which a first power supply voltage is applied and an input signal is supplied to amplify and output the input signal, and a second buffer section to which a second power supply voltage is applied and a signal output from said first buffer section is supplied to amplify and output the signal outside through an output terminal, a switching element which has two terminals respectively connected to said output terminal and a ground voltage terminal and receives a control signal to change a conductive resistance, and a bias circuit for receiving the input signal or a signal output from said first buffer section, generating a control signal, and supplying the control signal to said switching element to control the conductive resistance of said switching element so as not to allow a potential of said output terminal to exceed a predetermined value.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

Abstract: A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan and functional clock signals adapted to the sequential circuits, which may have a variety of required timing diagrams.

Abstract: An input signal (IN) and a threshold signal (Vt) are coupled to an output terminal (2) via the base-emitter paths of first (Q1) and second (Q2) transistors having respective collector electrodes connected to a supply voltage source (3). The output terminal (2) is coupled to a source of reference potential (4) via a first resistor (Re) and is coupled via a second resistor (Rd) to a selected plate of a capacitor (C1) that is connected between the collector and base electrodes of the second transistor (Q2). Circuit impedances are scaled such that Re>Rd>R1 wherein Re and Rd are the values of the first and second resistors, respectively, and R1 is a component of the output impedance of the threshold signal source (5).

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: An input structure transmits legacy signals to internal logic of a low voltage integrated circuit. The input structure includes a first node coupled to both a resistor voltage divider and a capacitor voltage divider, both of which have center taps coupled together, and also to the internal logic. The capacitor and resistor voltage dividers function to divide the higher voltage logic level range associated with the legacy signals to the low voltage logic level range suitable for input to the internal logic.

Abstract: In a D.C. restoration circuit for a digital FM radio receiver, in which demodulated signals may be presented at the output of the demodulator as low-level differential signals superimposed on a variable D.C. level, the differential signal paths are capacitively coupled to the inputs of a comparator, and the voltage excursions at these inputs are clamped when the voltage between the inputs exceeds a predetermined value.

Abstract: An apparatus for sequencing turn-on and turn-off of power converters includes a first DC to DC converter responsive to a control signal for asserting a voltage supply signal and a sense circuit responsive to the output of said first converter to sense the level of voltage at the output of the first converter and to provide an enable signal in response to the output of said first converter when the first converter reaches a desired value. The apparatus further includes a second DC to DC converter responsive to said enable signal to provide a second supply voltage at a second different voltage level. The sequencing control has a circuit responsive to said second supply voltage and the first supply voltage, to short the second DC to DC converter to a reference potential.

Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A clamping circuit for clamping a circuit node during an initial circuit powerup interval includes a switching circuit and a switching control circuit. The switching circuit is an N-MOSFET with its drain and source terminals connected to circuit ground and the subject node sought to be clamped, respectively, and its gate terminal connected to the switching control circuit. The switching control circuit includes a number of N-MOSFETs which are interconnected in such a manner as to receive the power supply voltage and generate a switching signal which turns the switching circuit N-MOSFET on during an initial circuit powerup interval to clamp the subject node and then off after the power supply has reached a preselected minimum value. Upon initial circuit powerup, the switching control circuit self-triggers itself to turn the switching circuit on and clamp the subject node at ground potential.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An electronically controllable low capacitance active bus line terminator achieves low output terminal capacitances by connecting emitters of switch transistors directly to the output terminals. Termination resistors are connected directly between an output of a voltage regulator circuit and collectors of the switch transistors. Emitters of optional clamp transistors can be connected to bases or collectors of the switch transistors to limit or prevent "ringing" of bus conductors connected to the output terminals if the switch transistors are turned on. The bus conductors are thereby isolated from parasitic capacitances associated with the termination resistors and the collectors of the switch transistors when they are turned off.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: A clamping circuit has a differential amplifier having a pair of transistors for comparing a voltage of an output node and a constant clamp voltage. The pair of transistors has a common emitter node supplied with a constant current from a first current source. An output of the differential amplifier is supplied to a base of a transistor for charging the output node. The output node is discharged constantly by a second current source. The constant current from the first current source is twice as large as the constant current from the second current source. The first and second current sources are controlled and activated to generate the first and second currents according to a current control signal. The clamping circuit also has a current control circuit for setting a value of each of the first and the second constant currents. The current control circuit is controlled by a clamp control signal and selectively activates the circuit and second current sources.

Abstract: A circuit pulls up an integrated circuit input capable of receiving a low voltage, receiving a high voltage, or floating. The circuit includes a first MOS transistor connected between the input and the high voltage; a serial connection between the high and low voltages of a second, third, and fourth MOS transistor; a connection between the gates of the first and second transistors and the junction of the third and fourth transistors; and a connection between the input and the gates of the third and fourth transistors.