Abstract: A shift register unit and a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal; an output circuit, connected to the pull-up node and an output terminal, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node; a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and a reset signal control circuit, connected to a first reset terminal and the reset circuit, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal; the reset control signal is configured to control the reset circuit to perform a reset operation.

Abstract: The present application is directed to a level shifting circuit. In one form, a level shifting circuit includes a first inverter, a level shifting unit, and a fast driving unit. The first inverter is configured to invert an input signal received at an input node and to output an inverted input signal to a second input node. The level shifting unit is configured to perform amplitude up-shifting processing on a received input signal. The fast driving unit is configured to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal.

Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.

Abstract: Various implementations described herein are related to a device having level shifter circuitry configured to receive isolation control signals in a first voltage domain and provide an output signal in a second voltage domain that is different than the first voltage domain. The device may include isolation logic circuitry configured to receive a data input signal in the first voltage domain and then provide the isolation control signals to the level shifter circuitry in the first voltage domain based on the data input signal. The isolation logic circuitry may include control passgates that enable the data input signal to propagate to the level shifter circuitry via the isolation control signals.

Abstract: Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Abstract: An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.

Abstract: In one embodiment, an amplifier circuit may be configured with an output transistor that forms an output current and an output voltage at an output. The amplifier circuit may also include a reference circuit that may be configured to form a reference current that is substantially proportional to the output current. An embodiment of the reference circuit may also be configured to control a transistor to sink current from the output in response changes in the reference current.

Abstract: A system of stacking interlocking blocks can be configured into a series of states in order to capture and display both physical and virtual events or content. In some examples, the system includes the stacking interlocking blocks, a grid base having the stacking interlocking blocks stacked on top of the grid base in a physical configuration, and a user system. Each stacking interlocking block includes a block circuit. The grid base includes an embedded computing system configured, by virtue of communicating with each of the block circuits, to determine a position of each stacking interlocking block with respect to the grid base and in some cases both the grid base and the other blocks which have been detected by the grid base.

Abstract: Various implementations described herein are related to a device having a level shifting circuit that shifts an input voltage in a first domain to an output voltage in a second domain, and also, the level shifting circuit may shift the input voltage to the output voltage based on a first level shifting response. The device may also include a boost circuit that increases the input voltage and provides a boosted input voltage to the level shifting circuit so that the level shifting circuit shifts the input voltage to the output voltage based on the boosted input voltage.

Abstract: A semiconductor device having a first switching device and a second switching device respectively on a power supply side and a ground side of the semiconductor device, for driving a load of the semiconductor device, and a switching control circuit that controls switching of the first and second switching devices. The switching control circuit includes a signal output circuit that outputs a set signal and a reset signal for turning on and off the first switching device, respectively, in response to an input signal of the semiconductor device, a level shift circuit that shifts a level of each of the set and reset signals, a drive circuit that drives the first switching device in response to an output from the level shift circuit, and a power supply circuit including a plurality of transistors that are Darlington-coupled, and are configured to generate a power supply voltage of the signal output circuit.

Abstract: A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.

Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

Abstract: A level shifter including an input block that receives an input voltage swinging between a first ground voltage and a first power supply voltage and that connects one node of a first node and a second node to a first ground node, in response to the input voltage, a shifting block that mutually exchanges the voltage levels of third and fourth nodes in response to a current flowing through the one node, a pulse generator that generates a first pulse and a second pulse in response to the input voltage, a first transistor that directly connects the third node to the first ground node in response to the first pulse, and a second transistor that directly connects the fourth node to the first ground node in response to the second pulse.

Abstract: Multi-level buffers for biasing of radio frequency (RF) switches are provided. An RF switching circuit that includes a field-effect transistor (FET) switch, an impedance, and a multi-level buffer that provides a switch control voltage to a gate of the FET through the impedance is disclosed. The multi-level buffer receives a control signal to turn on or off the FET switch. Additionally, the multi-level buffer is implemented with stacked inverters that operate using different clock signal phases to pulse the switch control voltage in response to a transition of the control signal to thereby shorten a delay in switching the FET switch.

Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal.

Abstract: A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.

Abstract: A plus width modulation (PWM) signal generator is disclosed. The PWM signal generator includes a first signal generator providing a first signal, an output terminal, a first voltage generating circuit including connected to the first voltage generating circuit for providing a first present voltage according to the first signal, and a second voltage generating circuit connected to the first signal generator for providing a second present voltage according to the first signal. The first present voltage is earlier supplied to the output terminal than the second preset voltage, and after the first preset voltage continuously is provided for a period of preset time, the first voltage generating circuit stops providing the first preset voltage.

Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.

Abstract: The feedback loop of a switching power converter controller is provided with an averaging circuit that averages either an output voltage, an error signal, or a control voltage. Regardless of which feedback signal is averaged, the averaging occurs over a first cycle of a rectified input voltage to form an averaged signal that is used by the feedback loop in a subsequent cycle of the rectified input voltage.

Abstract: A level shifter for outputting an output voltage having a voltage level range different from a voltage level range of a received input voltage is disclosed. The level shifter includes: a current mirror configured to copy a reference current flowing through a first mirror transistor to a second mirror transistor; a current mirror control circuit electrically connected to the current mirror by a sink node and including a plurality of control transistors configured to control the current mirror; and an output circuit configured to output an output voltage based on a voltage level of the sink node, wherein a first control transistor of the plurality of control transistors receives the output voltage fed back to a gate terminal of the first control transistor, and a second control transistor of the plurality of control transistors receives an inverted output voltage fed back to a gate terminal of the second control transistor.

Abstract: This disclosure provides a gate driving circuit, which comprises: first P-channel, second P-channel, first N-channel and second N-channel transistors, each has a gate, a source, a drain, and a base connected to the source; an output terminal electrically connected to the drains of the second N-channel and P-channel transistors; wherein the source of the first P-channel transistor is connected to a first voltage source, and a first voltage is applied to its gate; the source of the first N-channel transistor is connected to a second voltage source, and a second voltage is applied to its gate; the source of the second P-channel transistor is connected to the drain of the first P-channel transistor, and a third voltage is applied to its gate; the source of the second N-channel transistor is connected to the drain of the first N-channel transistor, and a control voltage is applied to its gate.

Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement of transistors is opposite the second series arrangement of transistors. The output of the first series arrangement of transistors is coupled to a first node and selectively couples the first node to a first voltage based on an input signal. The output of the second series arrangement of transistors is coupled to a second node and couples the second node to the first voltage based on an input signal. The first node and the second node are coupled to the first voltage at different times. The series arrangements of transistors enables faster level shifting over conventional level shifters.

Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

Abstract: A buffer circuit includes a current mode circuit configured to generate output signals by converting a current path depending on input signals and configured to correct a swing width of the output signals by adjusting a current amount depending on a level of a compensation signal. The buffer circuit also includes a compensation signal generation circuit configured to detect a swing width variation of the output signals and configured to generate the compensation signal for correcting a swing width of the output signals to conform to a target value, depending on a detected swing width.

Abstract: An integrated circuit is provided that includes an output stage circuit. The output stage circuit includes an input node for receiving a digital input signal, a supply voltage node for receiving a supply voltage signal, a digital to analog convertor for converting the digital signal, an amplifier for amplifying the converted signal, a first/second and optionally third voltage regulator generating a first/second and optionally third voltage signal, and a greatest-voltage selector circuit for providing power to the amplifier. Two different voltages are provided to the DAC. The output signal can be a SENT signal. The circuit is highly robust against power-interruptions and EMI.

Abstract: A voltage level translator translates signals between first and second voltage domains. An output buffer for a channel thereof includes a first plurality of PFETs and a first plurality of NFETS that are coupled to provide staggering of the output signal. A supply difference sensing circuit can disable staggering when an input voltage supply is greater than or equal to a VCCI trigger for the output voltage supply.

Abstract: A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.

Abstract: A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.

Abstract: In a first example a voltage level-shifting device includes a level-shifting stage circuit. The level-shifting stage circuit includes a first level-shifting inverter circuit to invert a buffered input signal to drive a first internal node, a second level-shifting inverter circuit to invert a buffered inverted input signal to drive a second internal node, a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on the state of the buffered inverted input signal, and a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on the state of the buffered input signal.

Abstract: Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

Abstract: According to one embodiment, a semiconductor memory includes: a memory cell array provided in a first layer above a semiconductor substrate and including a plurality of memory cells; a first word line coupled to a first memory cell of the plurality of memory cells; a driver generating a voltage applied to the first word line; a first transistor including one end coupled to the first word line and the other end coupled to the driver; a first transfer gate line coupled to a gate of the first transistor and including a portion passing through the first layer, a second layer between the semiconductor substrate and the first layer, and a third layer above the first layer; and a first level shifter applying a voltage to the first transfer gate line.

Abstract: A level shifter is disclosed. The level shifter comprises a pulse generating circuit, configured to receive an input signal, and generate a plurality of first-level pulses having a pulse width shorter than a pulse width of the input signal, wherein the input signal swings over a first voltage domain; a pulse transforming circuit, coupled to the pulse generating circuit, configured to generate a plurality of second-level pulses corresponding to the plurality of first-level pulses; and a latching circuit, coupled to the pulse transforming circuit, configured to generate an output signal by latching a status of the output signal in response to the plurality of second-level pulses, wherein the output signal swings over a second voltage domain.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Abstract: Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.

Abstract: A semiconductor device including a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.

Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.

Abstract: Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.

Abstract: A level shifter includes a first output terminal and a second output terminal. After an output signal in a high level state is outputted from the first output terminal and an inverted output signal in a low level state is outputted from the second output terminal, a weak driving circuit is connected between the first output terminal and a power supply voltage, and a strong driving circuit is connected between the second output terminal and the power supply voltage. After the output signal in the low level state is outputted from the first output terminal and the inverted output signal in the high level state is outputted from the second output terminal, the strong driving circuit is connected between the first output terminal and the power supply voltage, and the weak driving circuit is connected between the second output terminal and the power supply voltage.

Abstract: The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.