Abstract: Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.

Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

Abstract: A high-voltage level shift circuit includes: a first high withstand voltage NMOS transistor driven by an on command; a second high withstand voltage NMOS transistor driven by an off command; a first PMOS current mirror circuit inputting a drain current of the first high withstand voltage NMOS transistor to a reference side; a second PMOS current mirror circuit inputting a drain current of the second high withstand voltage NMOS transistor to a reference side; a first NMOS current mirror circuit inputting an output current of the second PMOS current mirror circuit to a reference side; and an I/V signal conversion circuit receiving an output of the first PMOS current mirror circuit and an output of the first NMOS current mirror circuit to obtain an output control voltage signal.

Abstract: A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.

Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.

Abstract: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

Abstract: A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.

Abstract: A voltage level translation circuit includes a first energy storage unit, a second energy storage unit, a first voltage level translation unit, and a second voltage level translation unit. The first voltage level translation unit is configured to translate a first communication interface transmitting pin voltage signal to realize a first communication between a first communication interface transmitting pin and a second communication interface receiving pin. The second voltage level translation unit is configured to translate a second communication interface transmitting pin voltage signal to realize a second communication between a second communication interface transmitting pin and a first communication interface receiving pin. A multiple interface communication system is also provided.

Abstract: An apparatus and method for operating a level shifter circuit that receives an input signal of interderminate voltage level is disclosed. The level shifter circuit may receive the input signal from a circuit block coupled to a first power supply signal, and generate an output signal using a second power supply signal, different than the first power supply signal. The level shifter circuit may clamp a storage node included in the level shifter circuit, and isolated at least one circuit path included in the level shifter circuit in response to a determination that an isolation signal has been enabled.

Abstract: A bidirectional voltage translator shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The voltage translator includes first and second I/O terminals for receiving and outputting the first and second voltage signals, respectively, and first and second one-shot circuits connected to first and second output transistors, respectively. The outputs of the transistors are connected to the first and second I/O terminals, respectively, and also are fed back to the respective one-shot circuits. When the output of the voltage translator has a high slew-rate, the one of the first and second one-shot circuits that corresponds to the output modulates the gate voltage of the corresponding output transistor based on the feedback signal to control the slew-rate of the output.

Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.

Abstract: A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and the digital signal.

Abstract: An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

Abstract: A level shifter circuit includes: an input stage for receiving an input signal switchable between a first and a second input level and an output stage to produce a drive signal for the load that is switchable between a first and a second output level. A level translator translates the input signal switching between the input levels into the output stage switching between the output levels. A feedback element coupled to the output stage transfers to the input stage a feedback signal representative of the output level of the output stage. The input stage includes control circuitry sensitive to the input signal and the feedback signal for detecting undesired switching of the output stage between the first and second output levels occurring in the absence of input signal switching between the first and second input levels. The control circuitry inverts the output level of the output stage resulting from undesired switching.

Abstract: An electronic device including a universal serial bus type-C connector. The connector includes a first plurality of contacts and a second plurality of contacts. Each of the first plurality of contacts and each of the second plurality of contacts include a first layer formed of a first material and a second layer formed of a second material, the second layer over the first layer. The second layer is present in a first area of each of the first plurality of contacts and the second layer is absent from the first area of each of the second plurality of contacts.

Abstract: A level shift circuit including serially-connected first resistor and first transistor and serially-connected second resistor and second transistor, a protection circuit that receives signals at a first junction between the first resistor and the first transistor and a second junction between the second resistor and the second transistor, a latch circuit receiving an output of the protection circuit, serially-connected third and fourth transistors and serially-connected fifth and sixth transistors respectively connected in parallel to the first and second resistors, a switching time detection circuit that receives the signals at the first and second junctions and detects an occurrence of switching noise, and first and second logical AND circuits that receive outputs of the switching time detection circuit and the signals at the first and second junctions, and respectively control the fourth and sixth transistors.

Abstract: An galvanic isolator circuit is provided. The electronic isolator circuit includes a coil and a magnetic field (MF) sensor. The coil is coupled to a first circuit. The MF sensor is coupled to a second circuit, and disposed corresponding to the coil. The first circuit transfers a MF signal to the MF sensor via the coil. The MF sensor transforms the MF signal into an output signal and provides the output signal to the second circuit. Accordingly, the galvanic isolator circuit is capable of realizing functions for galvanic isolating by utilizing the coil and the MF sensor.

Abstract: Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.

Abstract: Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

Abstract: In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n?-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal.

Abstract: The present disclosure provides a semiconductor device including: a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from, the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.

Abstract: A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract: A high voltage output driver circuit includes a first regulator having a first input, a second input, and an output coupled to the second input, a second regulator having a first input, a second input and an output, a driver having a first signal input, a second signal input, a first control input coupled to the output of the first regulator, a second control input coupled to the output of the second regulator, a first control output, and a second control output, a first power transistor coupled to the first control output of the driver, and a second power transistor coupled to the second control output of the driver. An integrated circuit comprising the high voltage output driver does not require external bootstrap components, such as capacitors, nor the attendant extra pins required to connect to such external bootstrap components.

Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The selector configured to selectively transmit one of the first output signal and the second output signal according to the first input signal.

Abstract: A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal. A second transistor of the transistors of the second pair of transistors is coupled with an inverted input signal terminal. The transistors of the second pair of transistors are cross-coupled with the transistors of the first pair of transistors. The voltage level shift circuit also comprises a third pair of transistors. The transistors of the third pair of transistors are coupled with the transistors of the first pair of transistors and the transistors of the second pair of transistors. A first transistor of the third pair of transistors is directly coupled with an output signal terminal and second transistor of the third pair of transistors is directly coupled with an inverted output signal terminal.

Abstract: Various embodiments of the invention provide for a multi-input switch regulator that is controlled to selectively receive power from one of multiple power sources in order to extend the range of available battery voltages at which the regulator can operate. Certain embodiments accomplish this by using an internal adaptive control circuit to coordinate multiple high-side switches to operate with a low-side switch to generate a desired output voltage.

Abstract: A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

Abstract: The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range.

Abstract: A high voltage level shifter includes a first high-voltage P-channel metal oxide semiconductor (HVPMOS) transistor, a second HVPMOS transistor, a discharge transistor having a first native high-voltage N-channel metal oxide semiconductor (HVNMOS) transistor and a first low-voltage N-channel metal oxide semiconductor (LVNMOS) transistor connected in series, and an avalanche transistor having a second HVNMOS transistor and a second LVNMOS transistor connected in series.

Abstract: A driver circuit includes normally-on transistors (Q1, Q2), control circuits (1, 2) that control the transistors (Q1, Q2), a capacitor (4) connected between power source nodes (1c, 1d) of the control circuit (1), a power source (7) connected between power source nodes (2c, 2d) of the control circuit (2), a MOSFET (16) connected between the power source nodes (1d, 2d), a control circuit (3) that turns on the MOSFET (16) when an output voltage VO reaches approximately 0 V, and a startup circuit that includes a Zener diode (20) connected in parallel to the capacitor (4) and that can charge the capacitor (4) with a Zener voltage even when the MOSFET (16) is off.

Abstract: Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.

Abstract: A level shifter circuit with improved time response and a control method thereof are disclosed herein. The level shifter circuit includes the output stage circuit of a level shifter and a booster circuit. The output stage circuit of the level shifter includes a first pass switch configured to transfer a voltage level of the first power supply of the level shifter to an output node, and a second pass switch connected between a second power supply and the first pass switch. The booster circuit accelerates the switching operation of the level shifter by accelerating a time response during the turning on or off operation of the first pass switch using charge sharing between a first capacitor and the parasitic capacitance of the control node of the first pass switch, which occurs via a first switch.

Abstract: In a gate driver for driving a first transistor, the gate driver includes first, second and third push-pull circuits, in each of the push-pull circuits, two transistors are connected in series, an output terminal of the first push-pull circuit is connected to the gate of the first transistor, an output terminal of the second push-pull circuit is connected to the gate of a second transistor included in the first push-pull circuit and an output terminal of the third push-pull circuit is connected to the gate of a third transistor included in the first push-pull circuit.

Abstract: An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

Abstract: A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node. The first and second mirror units may provide a first voltage to the negative output node and the positive output node. The clamping block may receive a second voltage, and couple the positive output node and the negative output node with the first and second mirror units, respectively.

Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Abstract: A semiconductor device with impedance calibration includes a first channel circuit of a first channel and a second channel circuit of a second channel. The first channel circuit is configured to drive a first node in response to a flag signal, generate a start signal from a signal of the first node to execute a first calibration operation in response to a mask signal, and generate and output an end signal after termination of the first calibration operation. The second channel circuit is configured to generate a transmission start signal from the end signal to execute a second calibration operation.

Abstract: Provided are a level shift circuit, a gate driving circuit and a display apparatus. The level shift circuit includes: a third to a sixth transistor, sources and gates thereof being connected to a DC power source and an offset voltage terminal respectively; a seventh transistor, source and gate thereof being connected to a reference ground and the offset voltage terminal respectively; and a first to a second transistor, gates and sources thereof being connected to an input signal terminal and drain of seventh transistor respectively, wherein drains of third and fifth transistors are connected as a first output terminal which is connected to drain of the first transistor, drains of fourth and sixth transistors are connected as a second output terminal which is connected to drain of the second transistor. Common-mode voltage of two output terminals of the level shift circuit with respect to the reference ground is not reduced.

Abstract: An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal.

Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.

Abstract: A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Abstract: A DC-DC converter includes a high-side circuit supplied with a power supply voltage and a first internal reference voltage generated by a first regulator. The high-side circuit provides a current to an inductor, which is used for generating an output voltage. The first and second regulators each generate respective internal reference voltages. The second internal reference voltage is provided to a signal processing module, which controls the high side circuit so that the output voltage of the DC-DC converter corresponds to regulated target voltage level. The first and second regulators include a differential circuit comparing voltages and generating a corresponding comparison signal, a transistor for generating the internal reference voltage according to a gate voltage applied to its gate, and a circuit to change the gate voltage to reduce a signal amplitude of the comparison signal.

Abstract: According to one embodiment, a level shift circuit includes first through fourth transistors, a control circuit, and first and second generating circuits. The control circuit outputs a first voltage obtained by level-shifting an input voltage to a first terminal. The first transistor supplies a first electric current to the control circuit for outputting the first voltage to the first terminal. The second transistor increases the first electric current. The first generating circuit generates a first pulse signal for controlling the second transistor. The third transistor supplies a second electric current to the first terminal for generating a second voltage corresponding to a first supply of a low-potential side. The fourth transistor increases the second electric current. The second generating circuit generates a second pulse signal for controlling the fourth transistor.

Abstract: An integrated circuit with input voltage clamping circuitry for receiving an input signal from external devices is provided. The input voltage clamping circuitry may include a voltage splitting and clamping circuit, a selectively enabled transmission gate circuit, and a digitization and clamping circuit. The voltage splitting and clamping circuit may be configured to split the input signal into at least two separate components each of which is limited to a predetermined voltage swing. The transmission gate circuit may be selectively enabled to provide full rail signaling when the input signal has a power supply level that is below a predefined threshold. The digitization and clamping circuit may include a Schmitt trigger translation for converting the split signal components to a digitized signal that is clamped down to the predefined threshold.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions.