Abstract: Aspects of the present disclosure provide techniques and apparatus for current-mode analog signal filtering. An example filter circuit generally includes a current-mode amplifier. The current-mode amplifier includes a first amplifier including an input and an output; a first inverter including an input coupled to the output of the first amplifier and including an output coupled to a first feedback path, the first feedback path being coupled to a first input of the filter circuit; and a second inverter including an input coupled to the output of the first amplifier.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Abstract: A control circuit used in a switch mode power supply is provided. The control circuit has an error amplifier, a first compensation network having a first resistance and a second compensation network having a second resistance. The error amplifier has a first input terminal, a second input terminal and an output terminal. The first compensation network is coupled between the first input terminal and the output terminal of the error amplifier. The second compensation network is coupled to the first input terminal of the error amplifier. When the switch mode power supply enters the transient state, the control circuit increases the first resistance of the first compensation network or decreases the second resistance of the second compensation network.

Abstract: Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

Abstract: A vertical bounce detection system of an elevator system includes at least one sensor operable to detect vertical movement of an elevator car in a hoistway. The vertical bounce detection system also includes a processing system communicatively coupled to the at least one sensor and a memory system having instructions stored thereon that, when executed by the processing system, cause the vertical bounce detection system to determine a bounce energy level of the elevator car based on sensor data from the at least one sensor. The instructions further cause the vertical bounce detection system to compare the bounce energy level to a bounce condition threshold. A speed reduction of the elevator car is commanded to continue movement of the elevator car at a reduced speed based on determining that the bounce energy level exceeds the bounce condition threshold.

Abstract: An electrical circuit includes a configurable resistor and a reference resistor with a current source circuit coupled to provide a current to the configurable resistor and the reference resistor. An Analog-to-Digital Converter (ADC) is configured to convert voltages from the configurable resistor and the reference resistor to digital values. A calculation circuit is configured to calculate an adjustment for the configurable resistor from a digital reference value obtained from a reference resistor voltage and two or more digital values obtained from two or more voltages corresponding to two or more configurations of the configurable resistor. A sequencer adjusts the configurable resistor based on the adjustment calculated by the calculation circuit.

Abstract: An exemplary method and arrangement for balancing currents of power semiconductors. The arrangement including multiple power semiconductor units and a central control unit. Each power semiconductor unit includes a power semiconductor and the central control unit and the power semiconductor units are arranged in a bi-directional ring, in which the central control unit sends control information for the power semiconductor units in both directions in the bi-directional ring and each power semiconductor unit receives the control information in both directions and forwards the received control information.

Abstract: In an integration mode, since a switch becomes OFF, a positive feedback path from an output terminal of an operational amplifier to a positive input terminal is blocked. Therefore, oscillation can be prevented even when a voltage of a signal line connected to a reference voltage supply point varies due to an impedance of the reference voltage supply point not being 0. In the integration mode, a resistor and a capacitor function as a noise filter. Further, in a reset mode, a switch becomes ON, and charge is accumulated in the capacitor depending on a reference voltage of the reference voltage supply point.

Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

Abstract: A radio-frequency circuit has a signal processing unit for processing a symmetrical input signal, two signal inputs for receiving the symmetrical input signal, a connection which is used as a ground point for the symmetrical signal, and a line which connects the signal inputs and has a length which essentially corresponds to an odd-numbered multiple of half the wavelength of the input signal. A method for testing a radio-frequency circuit having a signal processing unit for processing a symmetrical input signal is additionally provided.

Abstract: A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor.

Abstract: A coupling apparatus having a first branch and a second branch is disclosed. The first branch generally comprises (A) a first switch group configured to connect an input signal to an output node through a first capacitor, and (B) second switch group configured to connect either (i) a second signal, or (ii) a ground voltage, to the output node through a second capacitor. The second branch generally comprises (A) a third switch group configured to connect the input signal to the output node through a third capacitor, and (B) a fourth switch group configured to connect either (i) the second signal, or (ii) the ground voltage, to the output node through a fourth capacitor.

Abstract: A first constant voltage is supplied to a variable capacitance in a switched capacitor, and the variable capacitance is effectively charged to the first constant voltage in each cycle of a sampling clock. A current generated by charging the calibration resistance is averaged, and a resultant current is compared against a current generated by applying a second constant voltage to a resistance. The capacitance value of the variable capacitance is adjusted in accordance with a result of the comparison. Thus the variable capacitance is calibrated so as to have a target value.

Abstract: Embodiments of the present invention may include an apparatus and method to reduce an output swing in each stage of a multi-stage loop filter while also maintaining a desired signal transfer function for each respective stage. A given stage of the loop filter may include an integrator, a feedback path, a first cancellation path, and a second cancellation path. The first cancellation path may be coupled to the output of the integrator. The second cancellation path may be coupled to a feedback path provided about the input and output of the integrator. A first cancellation signal may be injected into the first cancellation path to reduce the output swing of the integrator. A second cancellation signal may be injected into the second cancellation path to minimize a change in the integrator's signal transfer function caused by the first cancellation signal.

Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: A semiconductor circuit which can have stable input output characteristics is provided. Specifically, a semiconductor circuit in which problems caused by the leakage current of a switching element are suppressed is provided. A field-effect transistor in which a wide band gap semiconductor, such as an oxide semiconductor, is used in a semiconductor layer where a channel is formed is used for a switching element included in a switched capacitor circuit. Such a transistor has a small leakage current in an off state. When the transistor is used as a switching element, a semiconductor circuit which has stable input output characteristics and in which problems caused by the leakage current are suppressed can be fabricated.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A switch is capable of performing switching, while reducing distortion with respect to amplitude of a high frequency signal. The switch includes: an input terminal to which a high frequency signal is input; a first switching unit connected between the input terminal and a first output terminal and selectively outputting the high frequency signal through the first output terminal; and a second switching unit connected between the input terminal and a second output terminal and selectively outputting the high frequency signal through the second output terminal. Each switching unit includes an impedance transformer installed on a signal line, a bipolar transistor having an emitter grounded, a collector connected to the signal line, and a base receiving current according to a control voltage applied thereto; and a bipolar transistor having a collector grounded, an emitter connected to the signal line, and a base receiving current according to the control voltage.

Abstract: An integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window. The circuit includes a plurality of integration paths each corresponding to an integration operation. The integration paths share a same voltage/current converter and a same first switching mechanism for switching a signal to be integrated at an input of the converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving a resulting current via a second switching mechanism for selecting the path.

Abstract: An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.

Abstract: An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.

Abstract: Provided are an active resistance-capacitance (RC) integrator and a continuous-time sigma-delta modulator, which have a gain control function. The active RC integrator includes an amplifier, a first base resistor connected between a first input node and a positive input port of the amplifier, a second base resistor connected between a second input node and a negative input port of the amplifier, a first resistor unit connected between the second input node and the positive input port of the amplifier, and a second resistor unit connected between the first input node and the negative input port of the amplifier. A resistor network including resistors and switches is configured to vary an input resistance, so that an active RC integrator may have a gain control function.

Abstract: An active filter includes a first filter and a second filter. The first filter receives an input signal, and generates a first output signal by filtering the input signal. The second filter receives the first output signal during a time period adjusted based on a variation of a time constant of the first filter, and generates a second output signal by filtering the first output signal received during the time period. Therefore, a variation of a time constant is compensated by using post integration time control.

Abstract: A driver integrated circuit for driving at least one high voltage half bridge stage. The driver including a filter circuit for filtering a signal provided to the half bridge stage, a minimum pulse width of the signal being near a constant time of the filter, wherein the filter circuit prevents distortions introduced when the signal is at its minimum pulse width from being passed to the half bridge stage.

Abstract: A voltage-controlled capacitor and methods for forming the same are described. A mechanical conductor membrane of the voltage-controlled capacitor is movable to and from a first position and a second position. An amount of capacitance can vary with the movement of the mechanical conductor membrane. A microelectromechanical systems (MEMS) voltage-controlled capacitor can be used in a variety of applications, such as, but not limited to, RF switches and RF attenuators.

Abstract: An integrator is provided which can reduce a disturbance in the current waveform of a current DA converter in order to improve the SNR of a ?? modulator, for example. The integrator includes an operational amplifier, and feedback paths provided in parallel between the output terminal and inverting input terminal of the operational amplifier. In one of the feedback paths, an integrating capacitor and at least one resistor are connected in series. In the other feedback path, a second integrating capacitor whose capacitance value is smaller than that of the integrating capacitor is provided.

Abstract: A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (Vref, Vcm,ref) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

Abstract: Embodiments of the present invention relate generally to reconstruction filtering. In particular, embodiments enable highly linear, highly programmable, and easily reconfigurable reconstruction filters. Further, embodiments provide substantial power consumption, area, and cost savings compared to conventional solutions. For example, embodiments use all-passive filtering and substantially reduce active elements compared to conventional solutions. As a result, significant reductions in required area, noise, and power consumption can be achieved. In addition, embodiments perform filtering solely in the current domain, thereby eliminating the non-linear voltage-to-current conversion used in conventional circuits and enabling highly linear filtering. Furthermore, embodiments are highly programmable and easily reconfigurable without the use of tunable capacitors. As such, embodiments are very suitable solutions for multi-band multi-mode wireless transmitters.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: Provided are an active resistance-capacitance (RC) integrator and a continuous-time sigma-delta modulator, which have a gain control function. The active RC integrator includes an amplifier, a first base resistor connected between a first input node and a positive input port of the amplifier, a second base resistor connected between a second input node and a negative input port of the amplifier, a first resistor unit connected between the second input node and the positive input port of the amplifier, and a second resistor unit connected between the first input node and the negative input port of the amplifier. A resistor network including resistors and switches is configured to vary an input resistance, so that an active RC integrator may have a gain control function.

Abstract: An integrator and a circuit-breaker are disclosed, the integrator being in the form of a passive symmetrical low-pass filter having an integration capacitor. In order to make it possible to temporally integrate an electrical signal in an improved manner, it is proposed in at least one embodiment that provision be made of a differential amplifier having two amplifying elements each having an input, that the two amplifying elements be coupled to one another in order to generate a differential signal, that the inputs of the two amplifying elements be connected to one another via the integration capacitor, and that each amplifying element be positively fed back to its input via a feedback loop in such a manner that the two amplifying elements together form a negative input resistance in parallel with the integration capacitor.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.

Abstract: A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors.

Abstract: A neural recording system (100) and method (400) for neural encoding is provided. The system can include an ultra-low power neural encoder (120) for compressing spikes within a neural signal (110) to produce a pulse train (130) and wirelessly transmitting the pulse train to a spike sorter (140). Features of the neural signal can be encoded such that the timing between pulses and the number of pulses conveys features of the spike. The neural encoder can include an Integrate and Fire (IF) neuron 230 that performs spike detection and encodes at least one spike (112) of the neural signal. A leakiness aspect (232) and an adaptive aspect (337) can be included with the IF circuit for combining aspects of spike detection and spike sorting for suppressing noise, keeping power consumption low, and improving signal resolution.

Abstract: In a circuit identifier, an electrical circuit includes an output node to output an electrical signal. A resistor device and a capacitor device, electrically in series with the resistor device, receive at least a portion of the electrical signal. A counter device determines a time for the capacitor device to reach a predetermined charge and assigns a value to the time for the capacitor device to reach the predetermined charge. A processor or other system reads the value assigned by the counter device and identifies the capacitor from a predetermined list of capacitors. The identification of the capacitor identifies a revision of the circuit.

Abstract: A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors.

Abstract: An integrated circuit that includes a resistor module with improved linearity is disclosed. The resistor module includes a diffused resistor body of a first conductivity type; a first terminal and a second terminal, each making direct electrical contact with the diffused resistor body; a doped well of a second conductivity type substantially surrounding the diffused resistor body on all but one major surface of the diffused resistor body, the doped well having contact regions; a first amplifier connected to the first terminal and to one contact region of the doped well; and a second amplifier connected to the second terminal and to another contact region of the well, such that the first amplifier and the second amplifier are connected for power supply only to the first terminal and second terminal, respectively. The first and second amplifiers may be unity gain buffer amplifiers or inverting opamps.

Abstract: A circuit is disclosed that compensates for the non-linearity of a current mode real pole producing circuit used to generate poles and zeros in complex filter circuits. The non-linearity of the prior art is compensated by driving one end of the primary pole producing capacitor with a signal derived from the drain current and fed back so as to counteract the non-linearity factors.

Abstract: A sensor signal conditioning circuit and sensor system incorporating the same. In one embodiment, the signal conditioning circuit includes a DC-coupled detector that converts a sensor signal into a discrete level signal. An AC-coupled detector having a dynamic DC threshold input also converts the sensor signal into a discrete level signal and has a startup delay associated with the dynamic DC threshold input. The signal conditioning circuit further includes a device that inhibits the DC-coupled detector responsive to the dynamic DC threshold input reaching a specified threshold voltage level such that the AC-coupled detector provides the detected output during steady-state sensor operation.

Abstract: A voltage integrator, comprising a resistor (4) and a capacitor (5) connected in series between an input voltage (V) and ground, wherein the resistance (R) of said resistor and the capacitance (C) of said capacitor are adapted such that a voltage (Vc) across said capacitor approximates the integral of said input voltage (V). Means are provided for preventing said capacitor voltage (Vc) from falling below a lower limit, preferably zero, thereby ensuring automatic initialization of the integrator after each integration cycle.

Abstract: An automatic time constant adjustment circuit has an error detection circuit and a variable time constant circuit. The error detection circuit detects, based on the resistance of an error reference resistor and the capacitance of an error reference capacitor provided therein, a resistance/capacitance error resulting from a variation attributable to an IC process, and then outputs a control signal corresponding to the resistance/capacitance error. The variable time constant circuit includes a resistance portion, a capacitance portion, and a switch portion. The resistance portion is build with one or more resistors. The capacitance portion is build with one or more capacitors. The switch portion sets the time constant of the variable time constant circuit according to the resistance/capacitance error by connecting together one of the resistors of the resistor portion and one of the capacitors of the capacitor portion according to the control signal.

Abstract: Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate.

Abstract: An R-2R resistor circuit network 12 used in a filter circuit according to the present invention has a path through which each branch current flows to a next integrating capacitor and a path through which each branch current flows to a low impedance analog midpoint (ground potential) Vss. The path can be selected by digital control bit data Bn to B0 for each branch current. By this, a frequency characteristic of a filter using an integrator as a component may be changed with an accuracy of (½n+1)(Gm1)/Cf from (½n+1)(Gm1)/Cf to ((2n+1?½n+1)(Gm1)Cf. As a result, by setting the setting bit width to 7 (n=6), a variable range of the frequency characteristic of over one hundredfold may be easily realized.

Abstract: A switched capacitor integrator system includes an input cascoded amplifier circuit; a summing junction; an integrating switched capacitor circuit connected to the output of the input cascoded amplifier circuit and to the summing junction; the integrating switched capacitor circuit including an input switched capacitor circuit responsive to an input and connected to the summing junction; and a correlated double sampling capacitor circuit including an offset capacitor interconnected between the summing junction and the input of the input cascoded amplifier circuit.

Abstract: A loop filter for a frequency synthesizer provides a lower frequency pole with a smaller capacitor than conventional filters. The loop-filter comprises a resistor and a smaller capacitor in a series-feedback path, and a transconductor to sense a voltage across the resistor to either source or sink additional current proportional to the sensed voltage. The transconductor and the smaller capacitor may provide a larger capacitance. The loop filter also may comprise an operational amplifier having the smaller capacitor and the resistor in the series-feedback path to receive pulses from a charge pump. The filter may integrate the pulses and may generate a control voltage related to a width of the pulses.

Abstract: In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.

Abstract: A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Abstract: An integration circuit includes an input node for receiving an input charge, an integrator having an input terminal coupled to the input node, an output terminal and a first charge storage device coupled between the input and output terminals, an intermediate node coupled between the input terminal and ground, a second charge storage device having a first terminal coupled to the intermediate node and a second terminal coupled to an output node of the integration circuit and an isolation device coupled between the integrator and the second charge storage device for selectively isolating the integrator from the second charge storage device. During a first phase of operation, the isolation device is activated and isolates the integrator from the second charge storage device, and the input charge received on the input terminal of the integrator is stored on the first charge storage device.