Abstract: A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple inverters are used, making the design scalable to deep sub-micron with low supply voltages, a rail-to-rail output swing, and a relatively low output impedance and useful tolerance to capacitive loading. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband transconductor is coupled between the integrator input node and integrator output node. A resistor connects the amplifier output node and the integrator output, while a capacitor is coupled from the integrator input to the amplifier output. The conductance of the resistor (the reciprocal of the resistance, or 1/R) is selected to be substantially equal to the transconductance gm of the transconductor. A method for achieving clean transient pulse response is also described.

Abstract: A method and apparatus for minimizing errors in a sensor device due to signal amplitude variation are disclosed herein. A signal output from the sensor device is amplified and, thereafter, AC-coupled to a comparator such that the amplification and AC-coupling of the signal minimize offset shift-related errors associated with the sensor device. The signal can be coupled to eliminate offset shifts due to component mismatches, calibration, aging and/or temperature associated with the sensor device. An AC-coupled sensor signal conditioning circuit is utilized to amplify the signal through an amplifier and then AC-couple the signal to a comparator.

Abstract: Methods and systems for tuning an RC continuous-time filter are disclosed. In this regard a representative system for tuning an RC continuous-time filter includes a coarse-tuned resistive element coupled to an input of the filter for varying the cut-off frequency of the filter based upon process variations. The system also includes a MOSFET transistor coupled to the resistive element. The MOSFET transistor provides a resistance dependent upon a voltage offset provided to the gate of the transistor, wherein the resistance of the transistor offsets an adjustment in the resistance of the resistive element caused by temperature variations. The system also includes a voltage offset generator configured to provide the voltage offset to the transistor.

Abstract: A sample-and-hold amplifier circuit has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. Thus, sampling can be carried out so that first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the (&phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive.

Abstract: A variable time constant integrator includes an amplifier configured to generate an output signal, a capacitor coupled to provide feedback to the amplifier, and a variable gain element coupled to the output of the amplifier and to the capacitor. The variable gain element is configured to provide the product of a gain and the output signal to the capacitor. The variable gain element is also configured to receive an indication of a new value of the gain and to responsively set the gain equal to the new value of the gain. Adjusting the gain of the variable gain element adjusts the integrator's time constant.

Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.

Abstract: A component inaccuracy correction system has a current source capable of outputting two currents with a fixed ratio, a voltage dividing circuit formed on the integrated circuit having at least an output end capable of receiving a current of the current source to output a divided voltage, a reference voltage generator capable of receiving another current of the current source to output a reference voltage, a comparison circuit electrically connected to the output end of the voltage dividing circuit for receiving the divided voltage from the voltage dividing circuit and comparing the divided voltage to the reference voltage to create a corresponding comparison signal, and a correction circuit electrically connected to the comparison circuit for correcting component inaccuracies of the integrated circuit according to the comparison signal generated by the comparison circuit.

Abstract: Provided are integrator circuit topologies that enable continuous integration without reset of the integrator circuit. One such integrator circuit includes a first integrator and a second integrator, each of the two integrators having a non-inverting terminal. Each of the non-inverting terminals is connected to an input node to alternately receive an input current for continuous integrator circuit integration without integrator circuit reset. The inverting terminal of the second integrator can be connected to an inverting terminal of the first integrator. The non-inverting terminal of the second integrator can be connected to an output of the first integrator through a first capacitor, and an output of the second integrator can be connected to a non-inverting terminal of the first integrator through a second capacitor.

Abstract: A differential integrator that uses a matched resistor array to reduce integrating currents and thereby realize a long time constant. The differential integrator comprises a differential operational amplifier having inverting and noninverting amplifier input terminals, and inverting and noninverting amplifier output terminals, the amplifier output terminals form inverting and noninverting output terminals, respectively, of the differential integrator. The differential integrator also comprises a noninverting differential integrator input terminal and an inverting differential integrator input terminal. The differential integrator also comprises a resistor array that couples the noninverting differential integrator input terminal to the inverting and noninverting input terminals of the amplifier, and the resistor array also couples the inverting differential integrator input terminal to the inverting and noninverting input terminals of the amplifier.

Abstract: A switched capacitor circuit includes an operational transconductance amplifier, a feedback stage having a first switched capacitor and a first time constant, and a load stage having a second switched capacitor and a second time constant. The first time constant and the second time constant are equal to each other to improve settling of the circuit. The first and second switched capacitors are coupled to an output of the operational transconductance amplifier via transistors. The transistors are sized so that the time constants of the feedback and load section are equal. In a further embodiment, the time constant of the feedback section is made greater than the load section, to further improve settling. On-state resistance of the transistors are controlled with respect to transconductance of the operational transconductance amplifier to maintain smaller error.

Abstract: In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C1), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V1) is present at a voltage divider that includes a resistor (R2) and a circuit section (R1) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R1) is realized as a switched capacitor (C1), and the resistance (R2) is realized as an MOS transistor (T1).

Abstract: A method and circuit arrangement for processing analog signals in applications in which low energy consumption is of the essence. An integrator topology where the active charge-transferring element is preferably a source-follower-type transistor in which one input terminal is arranged so as to be substantially independent of the input signal and in which the essential signal path elements of the circuit topology are connected in a fixed manner. Preferably, the circuit arrangement is realized so that it comprises separate transistors for sampling and charge transfer. Thus it is possible to connect an input signal in a fixed manner in an input terminal of the sampling transistor, and an input terminal of the charge-transferring transistor can be connected in a fixed manner to a constant voltage. By using a signal processing circuit according to the invention, it is possible to avoid circuit non-idealities caused by parasitic capacitances.

Abstract: The present invention provides a long time constant integrator circuit as part of an integrated circuit. The integrator circuit is fully integrated on chip with no external capacitive or resistive components for enhancing the circuit's time constant. It achieves a −3 dB cut-off frequency of 1.6 Hz. The circuit is realisable on a very small area of silicon being formed by a bipolar process using npn transistors, resistive and capacitive elements. The integrator circuit comprises a transconductance stage as an input to an operational amplifier. The circuit design is fully differential and employs realisable resistors and capacitors.

Abstract: A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy, wherein a portion of the degradeable material remains exposed. A protective coating of resin is applied to the exposed portion of the degradeable material by preferably depositing a predetermined amount of protective material, such as an epoxy resin, a void near the exposed portion of the degradeable material. The protective material preferably migrates to fully cover the exposed portion of the degradeable material without covering the circuit component. Accordingly, the circuit component is protected from substantial changes in operation characteristics due to the protective material and likewise is protected from changes in operation characteristics due to degradation of the degradeable material resulting from exposure.

Abstract: A PCI reflected-wave communications bus has a plurality of individual signal lines. Each signal line is terminated with a resistive-capacitive filter to partially dampen voltage wave reflections.

Abstract: A signal processing circuit for a charge generation type detection device of the present invention includes a charge-voltage conversion circuit for converting a charge generated in the charge generation type detection device to a voltage. The charge-voltage conversion circuit includes: a first capacitor for storing the charge generated in the charge generation type detection device; an operational amplifier connected to the first capacitor to form a feed-back loop; and a first switch connected in parallel with the first capacitor for discharging the charge stored in the first capacitor. The first switch includes a first transistor for generating a first clock feed-through and a second transistor for generating a second clock feed-through, the first switch being configured so that at least a portion of the first clock feed-through is canceled by the second clock feed-through.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a scounter.

Abstract: An integrator circuit having a relatively large RC time constant includes a resistive element implemented with a field effect transistor operated in a sub-threshold mode. The size of the field effect transistor is selected, in addition to the sub-threshold gate voltage, to achieve a desired resistance value in a small area and without using bipolar devices. A differential integrator circuit includes two field effect transistors operated in a sub-threshold mode, with a capacitor connected between the output terminals of the two field effect transistors. A bulk drive circuit can be optionally used to reduce high frequency in the bulk.

Abstract: A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input capacitor. An operational amplifier is included having a non-inverting terminal connected to a ground reference terminal, an inverting input terminal, and an output terminal feedback connected to the inverting input terminal and held in a virtual ground condition by a parallel of first and second charge paths which are connected between the input terminal of the switched input circuit structure and the inverting input terminal of the operational amplifier and connected to the supply voltage reference and the ground reference, respectively.

Abstract: An apparatus includes a switching circuit, an integrator circuit having an input for receiving a first signal from the switching circuit, a sensing circuit having an input for receiving a second signal from the integrator circuit, and a control circuit having an input for receiving a third signal from the sensing circuit and an output for sending a fourth signal to the switching circuit. In certain applications, the integrator circuit includes a first integrator and a second integrator having an inverting terminal connected to an inverting terminal of the first integrator. The second integrator also includes a non-inverting terminal connected to an output of the first integrator through a first capacitor, and an output connected to a non-inverting terminal of the first integrator through a second capacitor.

Abstract: A nonlinear resistor circuit utilizes capacitively-coupled multi-input MOSFETs in order to enable integration thereof by a standard CMOS process, and which can realize two types of nonlinear resistance characteristics; i.e., A-type and V-type nonlinear resistance characteristics. The circuit includes a core circuit which comprises enhancement-type N-channel and P-channel MOSFETs with source terminals being connected with each other.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (3) is started to generate an integration value (ios). At a certain instant (t1), the analog integration operation is interrupted to start counting (2) clock pulses (Clk). A selected number (N;N2) of clock pulses (Clk) is counted to obtain a sub-period (T2). The analog integration operation is resumed at the end of the sub-period (T2) at the integration value (ios) reached at the start of the sub-period (T2). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, including: a first resistor and a first capacitor which are parallel connected; an operational amplifier; a terminal of a second resistor which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor and the first capacitor; a second capacitor, which is ffeedback-connected between the output of the operational amplifier and the inverting input; and an additional pair of resistors which are arranged so as to provide feedback between the output and the inverting input, a current signal arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

Abstract: A circuit arrangement, in particular in DECT systems, for the regeneration of an input signal containing characteristic digital data sequences with N>1 allowed discrete values per digital position, having conversion means that produce a regenerated digital output signal from the comparison of the input signal with at least N−1 reference level, at least one integration element for obtaining the at least one N−1 reference level by integration of the segments of the input signal consisting of the characteristic data sequences, a drivable switching means for the activation or, respectively, deactivation of the integration of the input signal, a checking means that respectively activates the integration process by driving the switching apparatus at the beginning of a characteristic data sequence in the signal curve and, when the end of the data sequence is recognized, deactivates it again in order to avoid a shifting of the at least N−1 reference levels, as well as at least one delay elem

Abstract: An isolation method and circuit for providing dc isolation between two circuits that may have different reference potentials. There is provided a control circuit having an output terminal for providing a reset signal of predetermined length on the output terminal. A circuit to be controlled having an input terminal is provided, the circuit to be controlled being reset when a signal on the input terminal is below a predetermined threshold. A capacitor is coupled between the output terminal and the input terminal, the plate of the capacitor directly coupled to the circuit to be controlled being normally at a relatively high voltage. A voltage source is coupled to the input terminal of the circuit to be controlled through the parallel combination of a resistor and circuitry for unidirectional transmission of current toward the voltage source, generally a diode.

Abstract: A delay circuit includes a reference voltage generation circuit for generating a reference voltage which changes to a prescribed voltage level during the operation of a comparison circuit, an RC delay stage for integrating an input signal, a comparison circuit for comparing an output signal from the RC delay stage and the reference voltage of the reference voltage generation circuit, and a logic circuit for buffering the output signal of the comparison circuit. Since the reference voltage is pulled to a prescribed voltage level only during a comparison operation, the reference voltage may accurately be maintained at the prescribed voltage level only when necessary free from the influence of other circuits and noises. A delay circuit with reduced current consumption which is capable of changing an output signal with fixed delay time independently of the influence of fluctuations of the power supply voltage and the input logical threshold value of a logic circuit in a succeeding stage is provided.

Abstract: A signal shaping circuit for shaping amplitude shift keyed digital pulses of a digital data stream is set forth. The digital data stream is comprised of a plurality of symbols from which the signal shaping circuit generates an output signal having sinusoidally shaped transition regions between logic level transitions of the digital data stream. The signal shaping circuit comprises an input lead receiving each of the digital pulses of the digital data stream. A delay circuit receives each of the digital pulses of the digital data stream at the input lead and, after a predefined time delay, outputs delayed digital pulses corresponding to each of the digital pulses received at the input lead. A ringing filter circuit having a linear response receives each of the digital pulses of the digital data stream provided from the input lead and each of the digital pulses provided at the output of the delay circuit.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: An integrated capacitance multiplier circuit utilizes a pair of field effect transistors, biased in a conducting state, as virtual resistances of a classic operational amplifier network for implementing a capacitance multiplier function. The two field effect transistors have different sizes from each other for attaining a given ON-resistance ratio. A biasing circuit provides independently adjustable biasing voltages for the two field effect transistors. At least one of the two biasing voltages produced by the biasing circuit can be made dependent on temperature according to a certain dependency law in order to exploit the capacitance multiplier circuit for temperature compensating an integrated RC circuit employing the virtual capacitance provided by the multiplier circuit.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: A small sensor circuit with reducible electric power consumption is formed by connecting inverting amplifiers comprised of CMOS inverters connected in an odd number of stages, in series to guarantee the linearity of the relationship between inputs and outputs, and connecting an impedance as a sensor between the inputs and outputs, or to an input.

Abstract: A circuit configuration for smoothing an input voltage includes two input terminals for receiving the input voltage. A negative-feedback amplifier has two inputs and an output. A capacitor is connected to one of the inputs of the amplifier. An output terminal is connected to the output of the amplifier. A converter element has a first terminal connected to one of the input terminals, a second terminal connected to the one input of the amplifier and to the capacitor, and a third terminal connected to the output of the amplifier.

Abstract: A low-pass filter circuit including a first sub-filter designed in integrated circuit technology. The first sub-filter includes high-impedance resistor elements and smaller capacitances. A second sub-filter preceding the first sub-filter is constructed with low-impedance resistor elements and higher capacitances.

Abstract: An active RC integrator filter with finite operational amplifier bandwidth can be compensated by biasing the operational amplifier input stage such that its transconductance becomes a function of the resistance. Thereafter, by inserting another resistance of the same material in series with the integrating capacitor, a zero results in the overall transfer function of the filter according to the present invention. In this manner, the passband peaking of the active RC integrator filter resulting from the integrator phase shift can be avoided.

Abstract: A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Abstract: A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

Abstract: A differential load amplifier for receiving two measurement currents from a differential piezoelectric sensor and outputting a voltage proportional to a useful signal measured by the sensor. The differential load amplifier includes a subtraction device for determining a difference signal between the two measurement currents received from the sensor, and an integration device including and an integration capacitor for integrating the difference signal determined by the subtraction device. The subtraction device includes a negative immitance impedance converter, and the integration device includes an operational amplifier connected as an integrator. The subtraction and integration devices may also be implemented by a differential current amplifier and an integration capacitor, respectively.

Abstract: A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

Abstract: An integrator circuit is disclosed which overcomes problems in the art described above. In accordance with the present invention, an integrator circuit includes a differential input transconductance stage which converts an input differential signal to a differential current at first and second internal nodes. These two internal nodes are buffered from an integrating capacitor by two pass transistors, the conductance of which is automatically adjusted in response to the voltage at the two nodes. In this manner, the first and second nodes act as nearly ideal current sources. Thus, the integrating capacitor sees a nearly infinite impedance, thereby allowing the integrator circuit to achieve a large RC time constant while employing relatively small internal resistances. Further, the integrator circuit is fully differential and includes a floating capacitor having equal leakages on each of its plates. Being responsive only to differential signals, the integrator circuit thus ignores common mode leakages.

Abstract: The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

Abstract: A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on a circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

Abstract: An integrator is disclosed that is capable of outputting the same integration result with respect to the same bit pattern even if there are fluctuations in the integrating period, semiconductor device process, or the power supply voltage. The disclosed integrator includes: (1) a first integrator having a first amplifier, for integrating a reference voltage during an integrating period, (2) a second integrator having a second amplifier, for integrating an input signal during the integrating period, and (3) control means for outputting a signal regulating a gain of the first amplifier to the first amplifier so that an output of the first integrator varies in correspondence with the integrating period, and for regulating a gain of the second amplifier by means of the signal.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: Herein disclosed are a mean value detecting apparatus and a mean value detecting integrated circuit, having a mean value detecting unit formed with a resistance and a capacitance for detecting a mean value of an input signal, and an offset voltage adjusting unit connected in parallel to the mean value detecting unit at a connecting point of the resistance and a capacitance of the mean value detecting unit. With the above arrangement, this invention allows a large reduction of a size of the circuit.

Abstract: A filter circuit that consumes very little electric power. The active filter is a linear inverter constructed by 1) an inverting amplifying portion composed of an odd number of MOS inverters serially connected, 2) a grounded capacitance connected between an output of the inverting amplifying portion and ground, 3) a balancing resistance having a pair of resistances for connecting an output of one of the MOS inverters, other than the last MOS inverter, to the supply voltage and the ground, respectively, and 4) a feedback impedance for connecting the output and input of the inverting amplifying portion. A coupling capacitance is connected to the input of the linear inverter and a plurality of filter circuits are connected to an input of the coupling capacitance.

Abstract: A circuit that can switch between a peak detect and an averaging mode is described. In a preferred embodiment, when the circuit is in a peak detect mode a first transistor is on and a second is off, enabling an amplifier in the circuit to produce a signal representative of the peak value of an input signal. In an averaging mode, the first transistor is off, and a second transistor turns on, disabling the output of the amplifier, and thus enabling the averaging mode components of the invention.

Abstract: A driver circuit especially for driving scan velocity modulation (SVM) coils or similar loads is characterized by low quiescent current loading and high peak output. The driver is coupled to an input signal varying between a quiescent signal level and a peak signal level. A transistor is coupled to a power supply and to the input signal, so as to conduct according to the input signal. A nonlinear element such as a diode is coupled in series with the emitter-collector junction of the transistor, and is biased to a voltage slightly less than a forward biased conducting diode voltage drop. Thus the diode has a higher resistance when the transistor is conducting at the quiescent signal level, and a lower resistance when the transistor is conducting at the peak signal level. The quiescent bias conditions are maintained by resistors in series and parallel with the diode. The driver may be configured as a complementary push-pull stage.

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract: A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.