Abstract: The present disclosure provides a fuse storage cell. The fuse storage cell includes a transistor and N fuse elements. The transistor includes a source, a drain, and a gate. Each fuse element of the N fuse elements includes a first terminal and a second terminal. The first terminal of the fuse element is electrically connected to the drain of the transistor, and the second terminal of the fuse is configured for inputting a read voltage or a programming voltage. N is a positive integer.

Abstract: Detecting the presence of a television signal embedded in a received signal including the television signal and noise. Either first-order or second order cyclostationary property of the signals may be used for their detection. When the first-order cyclostationary property is used, the received signal is upsampled by a factor of N, a synchronous averaging of a set of M segments of the upsampled received signal is performed, an autocorrelation of the signal is performed; and the presence of peaks in the output of the autocorrelation function is detected. When the second order cyclostationary property of the signal is used, the received signal is delayed by a fixed delay (symbol time), the received signal is multiplied with the delayed version, and a tone (single frequency) in the output is detected.

Abstract: Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

Abstract: A transformer arrangement for signal transmission is provided, the transformer arrangement having at least one transformer with a primary coil and a secondary coil and a controller. The controller is configured in a magnetization phase to control a first current to flow through the primary coil to increase until a predefined criterion is fulfilled, wherein the magnetization phase is longer than a time constant of the primary coil of the at least one transformer. The controller is configured in a voltage application phase to apply a voltage to the at least one transformer so that a second current flows through the primary coil, wherein the second current has a polarity which changes during the voltage application phase compared with the first current, wherein the voltage application phase is shorter than two times the time constant of the primary coil of the at least one transformer.

Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.

Abstract: A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: An electrical circuit and a procedure for tracking at least one input pulse width applied to the electrical circuit. The electrical circuit includes a threshold component (e.g., a comparator) arranged to provide an output pulse width based on whether an input to the threshold component exceeds a threshold. The circuit also includes a controller arranged to control the threshold of the threshold component, based on the at least one input pulse width applied to the electrical circuit, such that the output pulse width of the threshold component tracks the at least one input pulse width applied to the electrical circuit. The controller includes at least a switch, and the output pulse width tracks the at least one input pulse width by following or anticipating the pulse width. In one example embodiment the tracking is performed for a series of pulses of varied widths.

Abstract: A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: A receiver includes: an amplifier that amplifies a received broadband signal up to a predetermined level; a first switch that switches an output signal from the amplifier; a signal generator that generates a signal for controlling a switching operation of the first switch; an integration capacitor that integrates an output signal from the first switch; a comparator that compares an output voltage from the integration capacitor with a predetermined voltage; and a reset circuit that discharges electrical charges accumulated in the integration capacitor based on a comparison result from the comparator.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: There are provided a Schmitt trigger circuit that has hysteresis characteristics in which a release point and an operating point are determined based on a width of an inputted pulse.

Abstract: A frequency regeneration circuit according to the present invention compares a width of a single pulse of input data with a time width of a 1/n clock cycle defined by a phase difference of multi-phase clock signals (where n is a natural number) in order to regenerate a frequency that is 1/n of a rate of the input data.

Abstract: Noise reducing circuitry may be included in a pulse width modulation circuit. The pulse width modulation circuit may include a comparator adapted to receive an analog signal and a sawtooth signal and to compare such signals to generate a pulse width output. In general, the noise reducing circuitry may include a sawtooth signal generating circuit configured to generate a sawtooth signal including an up ramp and a sawtooth signal including a down ramp. A control circuit may be coupled to the sawtooth signal generating circuit for controlling the sawtooth signal generating circuit based on whether a relatively narrow or relatively wide pulse width is to be output by the pulse width modulation circuit. Methods for reducing noise in a pulse width modulation circuit may generally involve dynamically controlling a direction of ramp of a sawtooth signal that is to be input to the comparator of the pulse width modulation circuit.

Abstract: A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.

Abstract: A digital pulse width modulation device includes a counter, a first comparator and a second comparator, wherein the first and second comparators are connected in parallel with each other and in series with the counter. The counter is capable of sending a count signal to the first and second comparators simultaneously, starting a count when the counter receives a clock signal, and transmitting the count signal to the first and second comparators. If the first comparator receives a pulse duty width signal, the count of the count signal will generate a pulse output of the corresponding duty cycle. If the second comparator receives a total pulse duty length signal and the count of the count signal reaches a number of the total length, a clear signal will be outputted to the counter to reset the counter to zero, so as to achieve the effect of correcting the output pulse.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: A low noise oscillator includes a resonator 102 that is excited with a pulsed signal (i.e., an impulse of energy) to replace energy lost to parasitic resistive losses once every Nth period (where N=1, 2, 3 . . . ). The resonating signal is monitored by a level detector and when the signal falls below a predetermined threshold, the pulse generator outputs a pulse or adjusts pulse width, pulse amplitude (or both) of a pulsed signal to create the necessary impulse for application to the resonator to recoup losses resulting from resonator operation. A phase shifting circuit may be provided to ensure the pulses are time aligned with the resonating signal to reduce noise.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.

Abstract: A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.

Abstract: Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.

Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.

Abstract: Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal.

Abstract: In a circuit identifier, an electrical circuit includes an output node to output an electrical signal. A resistor device and a capacitor device, electrically in series with the resistor device, receive at least a portion of the electrical signal. A counter device determines a time for the capacitor device to reach a predetermined charge and assigns a value to the time for the capacitor device to reach the predetermined charge. A processor or other system reads the value assigned by the counter device and identifies the capacitor from a predetermined list of capacitors. The identification of the capacitor identifies a revision of the circuit.

Abstract: In one embodiment, a current regulator is configured to form a first signal representative of a current flow through a power switch and to use the first signal to determine an off-time of the power switch.

Abstract: A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.

Abstract: A backward pedaling detection circuit has a charging/discharging circuit for charging and discharging the external capacitor to meet the threshold voltage required by the hysteresis comparator, based on the input from the hall sensor. An internal pull-down circuit, based on the pedal speed, keeps the circuit from false triggering. A comparator with hysteresis (Schmitt trigger) sets the upper and lower threshold voltage and eliminates the effect of noise. AND gates act like switches to allow the selected signal to pass through.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: In one embodiment, a PWM controller is configured to form a control signal that has reduced noise. The control signal is used to adjust a frequency of a clock signal of the PWM controller.

Abstract: A PWM controller that effectively transitions between normal mode and green power mode is disclosed. A driver provides a normal drive signal during normal operation. A pulse width detector detects the pulse width of the PWM signal and if the pulse width drops below a threshold the normal mode drive signal will be turned off and a pulse ON time measurer will begin storing the pulse ON time. When the total ON time reaches a total ON time threshold or the output voltage drops below a voltage limit, a green mode drive signal will be output to the power converter. During green mode the driver will continue sending the green mode drive signal at intervals until a heavy load condition when the green mode drive signal will be shut off and the driver will resume sending the normal mode drive signal.

Abstract: Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.

Abstract: A new system and method is developed for reducing the crest factor of a signal. The system includes a large signal extraction module for receiving the input signal and the magnitude of the input signal to extract a large signal greater than a predetermined threshold ?; a large signal transformation module for converting the extracted large signal to a monotonically increasing concave function; a large signal filtering module for filtering the large signal transformed by the large signal transformation module to pass a predetermined band of the large signal; a delay means for shifting the phase of the input signal; and a combiner means for combining the signal output from the large signal filtering module with the input signal whose phase has been shifted by the delay means to reduce the crest factor of the input signal.

Abstract: Example embodiments are directed to an apparatus and method for measuring a pulse width. A side-band signal generator may be configured to receive a given data pattern and output a side-band signal by modulating a pulse width of the received data pattern in a test mode. A phase detector may be configured to receive the side-band signal and a reference clock signal, and output a pulse signal corresponding to a phase difference between the received side-band signal and the reference clock signal. A charge pump may be configured to receive the pulse signal and output an output voltage by increasing or decreasing the output voltage based on the pulse signal. A pulse width measurer may be configured to receive the output voltage of the charge pump and determine whether pulses forming the side-band signal have appropriate widths based on whether the output voltage is included in a desired reference voltage range.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external clock signal level lies above a sensitivity level of the clock generator circuit for at least the duration of a sensitivity time of the clock generator circuit, and generates the internal clock signal with a second level if the external clock signal level lies below the sensitivity level for at least the duration of the sensitivity time of the clock generator circuit. The control circuit controls the clock generator circuit such that the control circuit selects the sensitivity time of the clock generator circuit in response to characteristics of the external clock signal.

Abstract: A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, coupled to the PWM controller, detects a load of the electronic system according to the PWM signal and generates a decision value accordingly. The adjusting module, coupled to the PWM controller and the load detector, controls the PWM controller to adjust the PWM signal according to the decision value.

Abstract: Clock regulation apparatus for preventing a logic switching mechanism from operating incorrectly. The apparatus has a supply voltage input that receives a supply voltage, which is also applied to the logic switching mechanism, a comparison unit that outputs an error signal if the supply voltage value drops below a reference value, a clock signal input that receives a clock signal from a clock generator, and a clock suppression unit, which is coupled to the clock signal input and to the comparison unit, that has a clock output for outputting the clock signal and that suppresses or delays the clock signal for a duration of at least one clock period if the error signal exists.

Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: A driver circuit for driving a light source of an optical pointing device includes a first transistor coupled to the light source. The driver circuit includes a controller coupled to the first transistor for monitoring a first current through the light source, comparing the first current to a reference current, and generating a control signal based on a result of the comparison, wherein the control signal causes the first transistor to change the first current.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

Abstract: Even when variation in transistor characteristic, resistance or the like occurs during manufacturing, a noise component is always minimized. Each of k clock phase difference generating circuits 16–18 shifts a phase of a basic clock signal ADCK1 by a specified different value to obtain a clock signal ADCK2 and supplies the clock signal ADCK2 to an A/D converter. A k counter 19 successively selects the clock phase difference generating circuits 16–18 and stores a noise component in an output of the A/D converter measured by a noise measuring circuit 27 in a corresponding register. A comparator 25 compares k noise components and obtains the number j of the clock phase difference generating circuit giving a minimum value. A selection circuit 26 fixedly selects only the j-th clock phase difference generating circuit.

Abstract: A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.

Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: An instantaneous voltage dip detection device is provided with: all-pass filter (2) for phase shifting a supply voltage waveform (11) by 90°; a comparator 7 that outputs a signal when the supply voltage waveform (11) is smaller than a threshold (12) in regions of ?/4 to 3?/4, 5?/4 to 7?/4; a comparator (8) that outputs a signal when a phase shift voltage waveform (13) is smaller than a threshold (14) in regions of 0 to ?/4, 3?/4 to 5?/4, 7?/4 to 2?; an OR circuit (9) to which signals from the comparators (7), (8) are inputted; and a signal generator (10) for generating a voltage dip detection signal in response to an output from the OR circuit (9).