Abstract: Disclosed is a method for a radar-based fill level measurement according to the pulse transit time method. Also disclosed a fill level measuring device for carrying out said method. On the basis of an evaluation signal, the relation between the clock rate and the sampling rate, and a predefined target relation, an evaluation curve is generated. The fill level is thereby determined on the basis of said evaluation curve. The evaluation curve is generated by means of temporal expansion or compression of the evaluation signal, wherein the compression or the expansion is carried out as a function of a ratio between the measured relation and the target relation. Any deviation of the sampling rate from the setpoint value of the sampling rate, for example due to faulty control, is compensated. Thus, the potentially attainable accuracy of the fill level measurement is increased due to the invention.

Abstract: Systems and methods of linearizing a signal of a light detection and ranging (LiDAR) sensor are described herein. A system receives a portion of a non-linear chirp signal. The portion of the non-linear chirp signal is sampled at a sampling frequency to generate data points corresponding to the portion of the non-linear chirp signal. A profile of the non-linear chirp signal is generated based on the data points. The non-linear chirp signal is linearized based on the profile of the non-linear chirp signal.

Abstract: Systems and methods are provided for resetting a qubit comprising a superconducting loop and a compound Josephson junction. A first bias flux is provided to the superconducting loop. A second bias flux is provided to the compound Josephson junction. Each of the first bias flux and the second bias flux are provided such that a given excited state of the qubit is near a top of a potential barrier associated with a potential of the qubit. A continuous microwave signal is generated having a frequency equal to a transition frequency between an other excited state of the qubit and the given excited state.

Abstract: An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

Abstract: An antenna driving apparatus drives an antenna by applying to the antenna a drive voltage having a rectangular waveform switching between a high voltage value and a low voltage value in a predetermined cycle. The antenna driving apparatus includes a high-voltage side switch, a low-voltage side switch, a duty ratio acquisition unit, a drive voltage application unit and a duty ratio switching unit. The duty ratio acquisition unit acquires a set value of a duty ratio as a time ratio at which the drive voltage is at the high voltage value in the rectangular waveform. The drive voltage application unit applies to the antenna the drive voltage by repeating execution of turning the high-voltage side switch into the nonconductive state. The duty ratio switching unit alternately executes switching of the duty ratio between a first duty ratio and a second duty ratio.

Abstract: A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

Abstract: An evaluation circuit for a capacitive sensor for detecting the distance, speed, or position of an object, comprises a reference capacitance and a measuring capacitance. A square wave voltage is applied to the reference capacitance and the measuring capacitance via a resistor, and a pulse which has a variable duration is obtained with the aid of a logic linking unit. The reference capacitance is connected to a first switching stage and the measuring capacitance is connected to a further switching stage. A single measuring capacitance has a capacitive coupling to an auxiliary electrode, and the switching stages are part of a logic linking unit. An output of the logic linking unit is connected to an integration stage. A charging capacitor (Ca) is charged or discharged via an output of the integration stage.

Abstract: Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit.

Abstract: A programmable load transient circuit includes a switchable power device for coupling a DUT output to its non-control node in series with a current sense device. A feedback loop is between the current sense device and the power device's control node that includes an integrator including an amplifier coupled to receive a signal that is a function of an average load current (IDavg) supplied by the DUT from the current sense device and to receive a reference voltage (Vref). The integrator provides an output drive voltage that is coupled to an input of a level shifter which receives a pulse signal or DC level at another of its inputs. The level shifter provides an output waveform or DC voltage to the power device's control node that is a function of IDavg.

Abstract: A communication apparatus includes a first terminal that receives a reference voltage, a second terminal that receives a pulse signal, and at least one processor to execute instructions. The instructions are executed to generate a clock signal that has a frequency higher than a frequency of the received pulse signal, count a number of pulses of the clock signal and determine a count value counted during a first cycle that is a cycle of the pulse signal to the second terminal, and, during a period of data transmission, increase or decrease an electric current that flows between the communication apparatus and the external apparatus according to a data value of data to be transmitted to the external apparatus. Data is transmitted to the external apparatus at least once during the first cycle, and data switch timing during the first cycle is based on the count value.

Abstract: A timing device includes a counter that performs counting action in synchronization with pulses in a clock signal to generate a 6-bit count value representing decimal numbers “0” to “39” in each count cycle in order to perform counting action on a 1/100-second basis and an output control circuit that outputs upper 4 bits of the count value generated by the counter as 4-bit timed data representing time on a 1/1000-second basis.

Abstract: The present invention relates to an evaluation circuit for a capacitive sensor for detecting the distance, speed or position of an object, comprising a reference capacitance and two measuring capacitances, wherein the reference capacitance and the measuring capacitances are supplied with a square-wave voltage via a resistor, and wherein by use of a logic unit a time variable pulse is obtained the duration of which is a measure for the respective measuring capacitance.

Abstract: A radio frequency transmitter for wireless communication includes a plurality of input ports to receive a plurality of sequences of baseband symbols to be transmitted on a plurality of disjoint frequency bands, a power encoder to modulate and encode the plurality of sequences of baseband symbols to produce an encoded multi-band signal including the plurality of disjoint frequency bands carrying the plurality of sequences of baseband symbols, a first power amplifier for amplifying the encoded multi-band signal to produce an amplified encoded multi-band signal, a first noise canceller to generate a first noise mitigation signal from the encoded multi-band signal and the plurality of sequences of baseband symbols, a first power combiner to combine the amplified encoded multi-band signal and the first noise mitigation signal to produce an RF multi-band signal, and an antenna for transmitting the RF multi-band signal.

Abstract: A circuit breaker is disclosed for an electrical circuit. The circuit breaker includes a tripping unit; at least one current sensor; and an input for a signal, at which a blocking signal for a circuit breaker arranged upstream on the energy sink side, can be received. The tripping unit; at least one current sensor; and an input are all connected to a control unit. A connectable blocking function is provided. The ascertained current is compared with a first current limit value, the exceeding of which requires this first current value to be present for a first period of time in order to prompt interruption of the electrical circuit; and is compared with a second current limit value. Different periods of time need to be present to prompt interruption when the blocking function is disengaged or engaged.

Abstract: Methods and apparatus embodiments to communicate data via a digital isolator by receiving an input data stream having first and second states, generating a first pulse train for the first state and a second pulse train for the second state. The first and second pulse types are transmitted across a voltage barrier of a digital signal isolator and received by a receive channel. The first and second pulse trains are processed to recover the input data stream in an output data stream. Data/System integrity functionality can identify fault conditions from an alteration of transmitted pulses.

Abstract: The invention discloses the technology of brain-like computing virtualization. Brain-like computing means the computing technology to mimic human brain and generate human intelligence automatically with computer software. Here the unconscious engine and conscious engine are used to define human left and right brain, while the virtualization technology is used for software to run on future hardware, such as quantum computer and molecular computer. The applied domain areas include quantum gate and adiabatic quantum simulation, brain-like autonomic computing, traditional multi-core-cluster performance service, software development/service delivery systems, and mission-critical business continuity/disaster recovery.

Abstract: A switching mode power supply generating reduced high frequency noise. The power supply includes a solid state switch, a modulator for driving the solid state switch with a periodic pulse drive signal, an output filter at the output of the solid state switch, where the output filter includes an inductor and a catch diode. A damping element is included for damping current spikes through the catch diode when said solid state switch turns on and thus reduce noise pulses that would otherwise be introduced by the current spikes.

Abstract: According to techniques of this disclosure in various examples, a wireless signaling system may include a stationary element such as a stator and a non-stationary element such as a rotor. The stationary element includes a stationary element controller. The stationary element is configured to transmit a wireless signal comprising a pair of pulses. The non-stationary element comprising a non-stationary element controller. The non-stationary element is configured to receive the wireless signal from the stationary element controller, measure a transition in voltage of each of the pulses and a time interval between the pulses, and interpret a signal based on the transition in voltage of each of the pulses and the time interval between the pulses.

Abstract: Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.

Abstract: Disclosed herein is an image pickup circuit including: amplifying means for amplifying a charge corresponding to an amount of light received by a photodetector, and outputting a pixel signal; ramp signal generating means for generating a ramp signal whose voltage drops with a fixed slope from a predetermined initial voltage; and comparing means for comparing the pixel signal output by the amplifying means with the ramp signal output by the ramp signal generating means. A reference potential of the pixel signal output by the amplifying means and a reference potential of the ramp signal output by the ramp signal generating means are at a same level.

Abstract: A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

Abstract: A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a ?2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the ?2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

Abstract: An RF tag system is provided, in which in addition to a method of easily sending back MPSK modulated sub-carrier signals on the RF tag side, communication protocols and circuit systems for accurately demodulating modulated waves on the RF tag reader side can be implemented, data transmission from an RF tag to an RF tag reader can be realized over a long operating distance at high speed, and an RF tag can be operated for a long lifetime.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to determine a first shaping level corresponding to applying a first shaping operation to data to be stored to the non-volatile memory. The controller is further configured to, in response to the first shaping level exceeding a threshold, perform a second shaping operation to generate shaped data that corresponds to the data, the shaped data having a second shaping level that is less than the threshold.

Abstract: A transmitter includes a first digital up-converter for converting data to an intermediate frequency (IF) signal, a pulse width modulator (PWM) for encoding the IF signal to an IF pulse train, a second digital up-converter for converting the IF pulse train to a radio frequency (RF) pulse train, a power amplifier for amplifying the RF pulse train; and a filter for reconstructing a RF analog signal from the amplified RF pulse train.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A method for utilizing heat includes steps: converting heat to electrical power, and converting the electrical power to a PWM voltage signal to power a function module. Obtaining an input voltage of the function module and comparing the input voltage with a reference voltage. Increasing a duty cycle of the PWM voltage signal when comparing the input voltage is grater than the reference voltage. And decreasing a duty cycle of the PWM voltage signal when comparing the input voltage is less than the reference voltage.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: A pulse width modulator has a first clock source providing a clock signal to a set input of an output controller configured to set a pulse width output signal and having a reset input to reset the pulse width output signal. A duty cycle control unit is coupled with the reset input of the output controller, wherein the duty cycle control unit has a numerical controlled oscillator (NCO) being coupled with a register and configured to provide for a direct digital synthesis to produce a specified frequency according to a value set in the register. Furthermore, logic is provided for receiving a signal from a second clock source and the pulse width output signal to trigger the numerical controlled oscillator.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: There is provided a two-wire transmitter which is connected to an external circuit by two transmission lines and which outputs a certain current signal to the external circuit using the external circuit as a power source. The two-wire transmitter includes: a sensor configured to convert a physical quantity into a first electrical signal and output the first electrical signal; a signal processing circuit configured to perform certain processing on the first electrical signal and output a second electrical signal; a constant current circuit configured to determine the certain current signal to be output to the external circuit, based on the second electrical signal; a reference voltage output unit configured to output a reference voltage based on the second electrical signal; and a shunt regulator circuit configured to determine a circuit voltage of the two-wire transmitter based on the reference voltage.

Abstract: A method and tag for decoding a signal received from a radio frequency identification (“RFID”) reader. A signal is received from the RFID reader in which the signal has a series of pulses. A time frame between receipt of two consecutive pulses is measured to determine whether the pulses represent zero bits or one bits. A total pulse duration is calculated in which the total pulse duration represents a sum of the measured time frames for the signal. A command is decoded. The decoding is based on the total duration of the two pulses.

Abstract: Groups of phase shifted Pulse Width Modulation (PWM) signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: The invention includes a method for transmitting and detecting high speed Ultra Wideband pulses across a wireless interface. The transmitter includes a serializer and pulse generator. The receiver comprises a fixed delay line, multiplier, local serializer (with a sequence matching the transmitter), digital delay lines, low noise amplifier and logic fan-out buffer along with an array of D flip-flop pairs. Each flip-flop pair is enabled, at fixed time increments, to detect signals at a precise time; the timing is controlled by the pseudo-random sequence generated by the local serializer. A local tunable oscillator is controlled by detecting the phase change of the incoming signal and applying compensation to maintain the phase alignment and clock synchronization of the receiver to the clock reference of the transmitter. The invention uses a pair of pulses with a fixed delay and then relies on mixing the two to provide better noise immunity.

Abstract: A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.

Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals.

Abstract: Provided are transmitter topology, receiver topology and methods for generating and transmitting a radio signal at a transmitter and detecting and processing a radio signal at a receiver. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: A modulator using a polynomial interpolator is described herein. In a simple circuit implementation of the modulator, coefficients of a representative polynomial are generated with interpolation filters in the polynomial interpolator. Crossing points may be identified for each sampling period by incorporating a virtual carrier waveform with the representative polynomial to generate a switching output control. Among other applications, the described modulator may be used in a Class-D amplifier. The described implementations may further confer benefits such as micro-power low voltage operation, low sampling rate, and low harmonic distortion.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.