Abstract: In accordance with an embodiment, a method of operating a transistor includes: switching the transistor on and off based on a control signal; monitoring a voltage of a collector node of the transistor; detecting whether the voltage of the collector node of the transistor is above a first threshold; and after detecting the voltage of the collector node of the transistor above the first threshold, regulating a voltage across a load path of the transistor to a first target voltage.

Abstract: A converter has a control element with a motion control function and a power element with a power semiconductor switch. The power element is provided with a safety control circuit that provides for a safety function.

Abstract: In one example, a method includes determining that an insulated-gate bipolar transistor (IGBT) is saturated, and while the IGBT is saturated, determining a collector-emitter saturation voltage (VCESat) of the IGBT.

Abstract: Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof.

Abstract: A semiconductor device includes an IGBT cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the IGBT cell in a lateral direction. Each of the two trench portions or each of the two trenches has a wide part below a narrow part. The wide parts confine a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction. The narrow parts confine a first-type doped mesa region of the first-type doped region at least in the lateral direction. The desaturation channel region has a width smaller than the mesa region in the lateral direction, and adjoins the mesa region.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: The invention relates to a switching power circuit connected to a motherboard of a computer system. The switching power circuit includes a PWM circuit and a snubber circuit. The PWM circuit includes a phase terminal, and it may output an output voltage to the motherboard via the phase terminal. The snubber circuit includes a zener diode. A negative terminal of the zener diode is connected to the phase terminal, and a positive terminal is connected to the ground terminal. The level of a breakdown voltage of the zener diode is equal to the level of the output voltage in a steady state.

Abstract: A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts.

Abstract: The invention concerns a method for controlling a switching assembly comprising a plurality of transistors connected in parallel, having a linear operating mode, a closed-switch operating mode and an off operating mode including a first operating phase during which a current flows from a source terminal to a drain terminal and a second operating phase during which no current flows. The method includes the following successive steps; (a) controlling the switching assembly in closed-switch mode during part of the first phase; (b) controlling the switching assembly in linear mode; (c) controlling the assembly in off mode during part of the second phase.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: An apparatus and method for driving a semiconductor switching element. The apparatus is configured to monitor at least one state variable of the semiconductor switching element, to switch off the semiconductor switching element in at least two stages, and to receive both a first parameter and a second parameter, the first and second parameters affecting how the state is monitored. The apparatus is further configured to receive both a third parameter and a fourth parameter, the third and fourth parameters affecting a two-stage switching-off operation of the semiconductor switching element.

Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.

Abstract: A circuit comprising a voltage-controlled transistor (T4), comprising a first (+) and a second (?) supply potential (+,?); a first (Ti) and a second transistor (T2); and an impedance (R4). A series circuit (R4, Ti) is formed by a switching path of the first transistor (T1) and the impedance (R4) is coupled between the first supply potential (+) and a control input of the voltage-controlled transistor (T4). The impedance (R4) is connected in a manner facing the first supply potential (+). The first supply potential (+) is coupled to a control input of the first transistor (T1) via to a switching path of the second transistor (T2). A control input of the second transistor (T2) is coupled to a connecting node (Vi) between the impedance (R4) and the switching path of the first transistor (T1) in such a way that a potential change at the connecting node (VI) can switch the second transistor (T2).

Abstract: The invention relates to a MOSFET circuit having reduced output voltage oscillations, in which a smaller CoolMOS transistor (T2) with a zener diode (Z1) connected upstream of its gate is located in parallel with a larger CoolMOS transistor (T1), so that, during a switch-off operation, after the larger transistor has been switched off, the smaller transistor (T2) carries a tail current on account of the zener voltage still present, which tail current attenuates output oscillations of the voltage.

Abstract: We describe a switching power converter comprising a bipolar switching device (BJT or IGBT) switching an inductive load, and including a closed-loop control system. The control system comprises a voltage sensing system to sense a voltage on a collector terminal of the switching device and provide a voltage sense signal; a controller; and a drive modulation system coupled to an output of the controller for modulating a drive to the control terminal of said bipolar switching device responsive to a controller control signal; wherein said controller is configured to monitor changes in the sensed voltage during a period when said switching device is switched on and to control said drive modulation system to control the degree of saturation of said bipolar switching device when the device is switched on and hence improve turn-off times.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector currents. The drive circuit includes a circuit operable to apply a varying voltage value to the control terminal of the bipolar transistor. A current/voltage converter senses a collector current flowing in the power bipolar transistor and controls conduction of a first transistor responsive thereto, the conduction of the first transistor controlling the conduction of a second transistor so as to vary the control terminal voltage in proportion to the sensed collector current of the power bipolar transistor.

Abstract: A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors.

Abstract: An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.

Abstract: There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: The present invention provides a semiconductor switching circuit and a semiconductor device using the switching circuit that can maintain sufficient isolation characteristics even when dealing with high frequency signals. The semiconductor switching circuit includes a first semiconductor switching element connected between a first terminal and a second terminal, a second semiconductor switching element, one end of the second switching element being connected to one of the first and second terminals, and an open stub connected to the other end of the second switching element.

Abstract: There are included a switching circuit for flowing pulse electrical current through a primary winding of a transformer, a half wave rectification circuit or a full wave rectification circuit for extracting electrical current from a secondary winding of the transformer while this pulse electrical current flows, and an electrical current regulation circuit which controls the magnitude of the electrical current which is extracted from the secondary winding of the transformer according to the collector voltage of the power transistor. Since the most suitable pulse electrical current is made directly from the direct current power supply and is supplied to the base of the power transistor, there is no requirement to provide any DC-DC converter, and it is possible to reduce the size and the cost of the power supply circuit for driving the power transistor.

Abstract: The invention provides apparatus, methods and systems for providing voltage protection at the drain-to-source path of an output transistor. The invention discloses circuit apparatus and system giving excess voltage protection in a circuit having a voltage swing up to approximately twice the voltage capacity of a circuit output transistor. Methods of the invention disclose maintaining the source-to-drain voltage of a protection transistor coupled to the circuit output transistor below its maximum value, while also maintaining the protection transistor gate-to-source voltage below its maximum value. The drain-to-source voltage of the circuit output transistor is guarded from exceeding its maximum acceptable drain-to-source voltage value by the protection transistor. Also disclosed are methods of selecting a protection transistor and related components such that the bias of the protection transistor is adjusted in response to the circuit output.

Abstract: A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Abstract: In a switching circuit, a first electrical element (22) is disabled before a second electrical element (30) is enabled. The switching operation is called break before make and ensures that disabling operation of a first electrical element occurs before enabling operation of a second electrical element. The assurance is in the form of a disable signal being detected from a first electrical element at an input of a first detection circuit (28). Correspondingly, the detected disable signal of the first electrical element enables operation of the second electrical element. Alternatively, a detected disable from the second electrical element at the input of the second detection circuit (20) enables operation of the first electrical element.

Abstract: A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Abstract: Circuitry for amplifying a single-ended analog sensor output includes a field effect transistor (FET) having a gate connected to a first end of a capacitor, the second opposite end of which is connectable to the sensor output. The gate of the FET is also connected to a first end of a resistor and to a cathode of a diode. The anode of the diode, the opposite end of the resistor and the drain of the FET are connectable to a ground reference, and the source of the FET defines an amplifier output that is connectable to a constant current source. The capacitor, resistor and diode are operable to bias the FET to thereby prevent clipping of the output signal at the amplifier output. A high-pass filter is also provided at the second end of the capacitor, and a number of diodes are preferably included for providing for amplifier input protection, electrostatic discharge protection and output DC overvoltage protection.

Abstract: Method and circuitry for clamping outputs of inactive error amplifiers in battery chargers eliminate delays and prevent oscillatory tendencies. By clamping the output of, for example, an inactive current loop amplifier in response to the output of an active voltage loop amplifier in a battery charging circuit, the inactive amplifier is prevented from saturating, such that it can take over as the controlling loop with minimal delay.

Abstract: Electronic circuit including an electronic power switch, for example an IGBT, controlled at its own gate terminal by resistive means in order to reduce its switching speed. The circuit includes a voltage sensor for reading a measurement that is a function of the potential of the collector of the electronic switch, for example its variation over time. The resistive means have a resistance that varies according to the command signal applied to an input terminal of the circuit and to the measurement read by the voltage sensor.

Abstract: A circuit configuration for protecting a MOSFET against overvoltages, includes at least one diode connected in the blocking direction between a drain terminal and a gate terminal of the MOSFET to be protected. A series connection of a load path of a further MOSFET and a further Zener diode connected in the blocking direction, is connected between the at least one Zener diode and the gate terminal of the MOSFET to be protected. A cathode of the further Zener diode is connected to a gate terminal of the further MOSFET.

Abstract: Saturation of a bipolar power transistor is controlled by sensing the current which is eventually injected into the substrate of the integrated circuit by the saturating transistor and using this signal for exerting a limiting action on the current which is driven to the base of the power transistor by a dedicated driving circuit. Unlike the prior art antisaturation systems, it is no longer necessary to precisely monitor the operating voltages across the terminals of the bipolar power transistor. A suitable sensing resistance may be integrated conveniently at a distance from the often complex integrated structure of the bipolar transistor. The system of the invention offers numerous advantages and ensures intervention of the antisaturation circuit only when the power transistor has positively reached a state of saturation, but well before any unwanted consequence.

Abstract: A specification is given of a circuit arrangement for controlling a pulse output stage, which comprises a MOS-FET power stage and a controller stage. The controller circuit (5) is connected to the drain of the MOS-FET (1) as the sole voltage supply, and the parameters of the circuit arrangement are designed such that the voltage drop across the drain of the MOS-FET (1) does not exceed the permissible voltage maximum at the gate of the MOSFET (1). The supply current flowing from the drain of the MOS-FET to the controller circuit preferably contributes to the load current.

Abstract: An all npn totem pole TTL output stage is provided with an active regulation circuit that continuously senses the voltage level at the output terminal and feeds it back to control the drive signal that is applied to the base of the bottom output transistor to switch the output state of the load quickly without wasting transient current and then scale back the drive signal during steady state operation to minimize wasted current. When the load is driven into its output low state, the active regulation initially holds the drive signal at a high level so that the load switches quickly. Once the output voltage has fallen low enough, the active regulation reduces the drive signal such that the bottom output transistor is held on the edge of conduction and does not saturate. In this state, the bottom output transistor pulls the output voltage down to approximately ground without conducting any appreciable amount of current.

Abstract: An input signal processing circuit which prevents saturation of the input transistor. It has an input npn transistor QN1, a transistor QP1, the emitters of which are connected to the cathode terminal T.sub.CTD, and the collectors of which are connected to the collector of the input transistor. Transistors QP2,QP3 have emitters connected to the cathode terminal T.sub.CTD, and bases connected to the bases of transistor QP1. Transistor QN2 has its emitter connected to anode terminal T.sub.AND via resistor R5 and its collector connected to a common connecting point with the bases of transistors QP1,2. Transistor QN3 has its emitter connected to the anode terminal T.sub.AND, its base connected to the base of transistor QN2, and its collector connected to base and the collector of transistor QP2. A resistor R4 is connected between the collector of input transistor QN1 and the collector of third transistor QN2.

Abstract: The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.

Abstract: In a push-pull type logic apparatus including a push-pull buffer formed by two bipolar transistors, a control circuit for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit is provided for releasing the clamp operation of the voltage clamp circuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON.

Abstract: An integrated circuit output stage is intended for use with an operational amplifier. The output is capable of driving capacitive load to within a V.sub.SAT of the power supply rails. The complementary output transistors are driven by way of a combination of buffers and complementary differential amplifiers which act to bias the stage in class AB. The quiescent current is stabilized and controlled, in part, by simple resistor rationing. The output transistor saturation is sensed and a current limit is imposed so that hard saturation is avoided. Frequency compensation is achieved in a manner that responds to output transistor saturation so as to improve the high frequency transient response. Feedforward capacitors are also included to further improve high frequency response.

Abstract: A line driver switching stage includes a terminal for a reference potential, a terminal for a supply potential, and an output terminal of the line driver switching stage. A differential amplifier has a first and a second amplifier branch. The first amplifier branch has a resistor with first and second terminals. The first terminal of the resistor is the terminal for the reference potential. An emitter follower transistor has an emitter and has a base-to-emitter path connected between the second terminal of the resistor and the output terminal. A saturation prevention element has a first terminal connected to the output terminal and a second terminal connected to the second amplifier branch. A bipolar transistor has a base-to-emitter path connected between the second terminal of the saturation prevention element and the terminal for the supply potential. The bipolar transistor has a collector connected to the emitter of the emitter follower transistor.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: A load circuit which can tolerates large current and voltage swings before saturation begins includes a field effect transistor having a source coupled to a power supply, a drain coupled to an input terminal which receives signals from a memory circuit data line, and a gate coupled to the drain through a level shifter.

Abstract: A drive transistor has its base coupled to a circuit input and its collector coupled to provide an output current at a circuit output. The output current is responsive to a base current received at the base of the drive transistor. A voltage induced across a resistor connected between the circuit input and the base of the drive transistor indicates the amount of drive transistor base current. A portion of an input current presented at the circuit input is diverted to the circuit output based on the indicated amount of drive transistor base current. The remaining portion of the input current is provided as the drive transistor base current. The drive transistor is thus prevented from saturating.

Abstract: An integrated circuit which includes a detection circuit for detecting the condition of saturation of an output transistor (Q.sub.0) whose collector-emitter path is intended to pass an output current. A threshold circuit (A) of the detection circuit is arranged to perform a switching operation when a representative parameter of the condition of saturation crosses a given threshold. A control transistor (Q) is arranged to supply at least a part of the base current of the output transistor (Q.sub.0) and the threshold circuit (A) performs its switching operation when the value of the current passing through the collector-emitter path of the control transistor exceeds a given level.

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.