Accelerating Switching Patents (Class 327/374)
  • Patent number: 10320381
    Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 11, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Kathiravan Krishnamurthi, Jean-Marc Mourant, Olivier Hubert, Shawn Bawell
  • Patent number: 10200031
    Abstract: An electronically switchable diplexer (200), especially an electronically switchable diplexer (200) with low video crosstalk, comprises a low-pass terminal (210), a terminal (220) for feeding in a first control signal, a common terminal (230), a high-pass terminal (240), and a terminal (250) for feeding in a second control signal, wherein the low-pass path of the diplexer (200) operates down to DC (direct current).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 5, 2019
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Rudolf Forstmaier, Bernhard Schaffer
  • Patent number: 10148264
    Abstract: A semiconductor device drive circuit includes a first drive circuit and a second drive circuit. The first drive circuit generates a control signal for controlling a voltage-controlled switching element. The first drive circuit generates a control signal in synchronization with a voltage signal input to the first drive signal. The first drive circuit has an output current capability corresponding to a magnitude of the voltage signal. The second drive circuit outputs a voltage signal to the first drive circuit. The second drive circuit includes an output adjustment circuit that adjusts the magnitude of the voltage signal.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: December 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Hokazono, Akihisa Yamamoto, Dong Wang
  • Patent number: 10141842
    Abstract: The invention provides a power converter comprising: an input for receiving input power with a variable nominal mains level, wherein said variable nominal mains level falls within at least 90V to 240V; a main power switch (Q1) driven by the input power, and a control circuit (Q2, Q3) for controlling a control current of the main power switch (Q1), wherein the control circuit in (Q2, Q3) is adapted to sense the level of the input power and draw current from a control terminal of the power switch (Q1) according to the level, and said control circuit is adapted to operate in linear region and increase the drawn current along with the increase of the level throughout the variable nominal mains level of the input power, wherein the control circuit comprises: a Darlington bridge with a first transistor (Q2) and a second transistor (Q3), the first transistor (Q2) with a base terminal connected to a circuit position indicative of the voltage amplitude of the input power, the second transistor (Q3) with a base termina
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 27, 2018
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Xianhui Zhang, Ken K. Li, Zhi Quan Chen, Junhu Liu, Ace Li
  • Patent number: 10116292
    Abstract: There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiko Yokoi, Yusuke Ojima
  • Patent number: 9847774
    Abstract: Apparatus and methods for level shifting in a radio frequency system are provided. In certain configurations, a radio frequency system includes a level shifter operable to provide level shifting to an input signal. The level shifter is biased by a bias voltage and powered by a supply voltage and a charge pump voltage. The radio frequency system further includes a charge pump configured to provide the charge pump voltage and to receive a mode signal operable to enable the charge pump in a first state and to disable the charge pump in a second state. The radio frequency system further includes a level shifter control circuit configured to control the bias voltage to track the charge pump voltage when the mode signal is in the first state, and to control the bias voltage with the supply voltage when the mode signal is in the second state.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 19, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jonathan Christian Crandall, Kenneth Norman Warren, Philip H. Thompson
  • Patent number: 9806695
    Abstract: An integrated circuit device includes a clock gating circuit, which is configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals. A plurality of functional circuits are provided, which are responsive to respective ones of the first plurality of clocks. The plurality of functional circuits is configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-jo Kim
  • Patent number: 9806594
    Abstract: A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 31, 2017
    Assignee: MITSUBISHI CORPORATION
    Inventors: Yosuke Shinomoto, Michio Yamada, Kazunori Hatakeyama, Takuya Shimomugi
  • Patent number: 9712149
    Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shunichi Kaeriyama
  • Patent number: 9608627
    Abstract: A method of controlling electrical power delivery to a well tool can include transmitting trigger light via an optical waveguide to a circuit in a well, and the circuit delivering the electrical power to the well tool in response to the circuit receiving the trigger light. A circuit for supplying electrical power to at least one well tool can include a photodiode which receives light from an optical waveguide in a well, a voltage increaser which increases a voltage output by the photodiode, and an electrical energy storage device which receives electrical energy via the voltage increaser, whereby the electrical power can be supplied to the downhole well tool from the storage device.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 28, 2017
    Assignee: Halliburton Energy Services
    Inventors: Neal G. Skinner, David P. Sharp
  • Patent number: 9531373
    Abstract: A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. The first switch is electrically coupled between the first terminal and a voltage supply of the power transistor. A second terminal of the first capacitor is electrically coupled to the reference potential. The gate drive circuit further includes a first voltage limiter in parallel with the first capacitor. The first voltage limiter limits a voltage across the first capacitor to a first predetermined voltage. The gate drive circuit further includes a second capacitor, a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor. The gate drive circuit further includes a third capacitor with a first terminal electrically coupled to a second terminal of the second capacitor and a second terminal electrically coupled to a gate terminal of the power transistor.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: December 27, 2016
    Assignee: NXP USA, Inc.
    Inventors: Thierry Sicard, Philippe Perruchoud
  • Patent number: 9496866
    Abstract: A rising time detecting circuit detects a rising time of an output voltage, and generates a rising time voltage according to the rising time. A rising time comparing circuit compares the rising time voltage with a target rising voltage, and outputs a rising comparison signal showing a compared result. A FET driving circuit controls an upper MOSFET based on the rising comparison signal. A rising regulating circuit regulates a change speed of the rising time voltage according to a rising regulating signal.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 15, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tetsuya Masaoka
  • Patent number: 9444446
    Abstract: In a switching control circuit, a determiner determines whether there is one of a first type of abnormality and a second type of abnormality different therefrom in a target switching element and/or the switching control circuit. A controller controls a second switching element to close a low-impedance discharge path for discharging a control terminal of the target switching element when it is determined that there is the first type of abnormality, and disables closing of a high-impedance discharge path for discharging the control terminal while the low-impedance discharge path is closed by the second switching element. The controller controls a third switching element to close the high-impedance discharge path when it is determined that there is the second type of abnormality; and disables closing of the low-impedance discharge path while the high-impedance discharge path is closed by the third switching element.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 13, 2016
    Assignee: DENSO CORPORATION
    Inventor: Junichi Fukuta
  • Patent number: 9438230
    Abstract: A gate drive circuit in an aspect of the present disclosure includes a modulated signal generation circuit that generates a first modulated signal, a first isolator that isolatedly transmits the first modulated signal, and a first rectifier circuit that generates a first output signal by rectifying the first modulated signal. The first modulated signal includes a first amplitude, a second amplitude larger than the first amplitude, and a third amplitude larger than the second amplitude. The first output signal includes a first output voltage value according to the first amplitude, a second output voltage value according to the second amplitude, and a third output voltage value according to the third amplitude.
    Type: Grant
    Filed: April 19, 2015
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shuichi Nagai, Yasufumi Kawai, Daisuke Ueda
  • Patent number: 9413241
    Abstract: An apparatus for providing auxiliary power to an off-line switcher. The apparatus includes a high voltage semiconductor switch and a driver for the high voltage semiconductor switch. The driver includes a first switch, the first switch coupled to the a third terminal of the high voltage semiconductor switch and to ground, a second switch coupled to a first terminal of the high voltage semiconductor switch, a third switch coupled to the first terminal of the high voltage semiconductor switch and to ground. The driver further includes a diode, the anode of the diode coupled to the third terminal of the high voltage semiconductor switch and the cathode of the diode coupled to the second switch.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: August 9, 2016
    Assignee: Dialog Semiconductor Inc.
    Inventor: Andrey B. Malinin
  • Patent number: 9094012
    Abstract: A driving circuit of the present invention drives a switching element connected to a main current circuit. The driving circuit includes a driving potion applying on/off-voltage to a gate of the switching element, a common inductor disposed in an interconnection part commonly connected to the driving circuit and a source side of the switching element in a loop formed of the main current circuit and the switching element, and a capacitor connected between the gate side and the source side on the driving portion side with respect to the common inductor.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 28, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mituharu Tabata, Yuji Miyazaki
  • Patent number: 9054585
    Abstract: Embodiments of the disclosure relate to a low drop diode equivalent circuit. Piezoelectric device based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The low-drop-diode equivalent can replace the rectifier diodes and minimize power loss. The diode equivalent mimics a diode using linear region operated MOSFET. The diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a value which gives an overall output power improvement. The diode equivalent replaces the four diodes in a full wave bridge rectifier, which is the basic full-wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 9, 2015
    Assignees: Department of Electronics and Information Technology, Indian Institute of Science
    Inventors: Bharadwaj Amrutur, Laxmi Karthikeyan
  • Patent number: 9030252
    Abstract: A high frequency switch device includes a branch transmission line corresponding to each output terminal provided with a switching part. In the branch transmission line, the switching part includes a transmission side diode provided in such a manner that a cathode thereof is arranged on a side of an input terminal 41 and an anode thereof is arranged on a side of the output terminal, and a ground side diode provided in such a manner that a cathode thereof is grounded and an anode thereof is electrically connected between the output terminal and the transmission side diode in the branch transmission line. The branch transmission line includes a first capacitor and a second capacitor on the side of the output terminal from the transmission side diode in such a manner that the anode of the ground side diode is connected between the first capacitor and the second capacitor.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 12, 2015
    Assignee: Imagineering, Inc.
    Inventors: Minoru Makita, Yuji Ikeda
  • Publication number: 20150116022
    Abstract: A half bridge circuit including an isolation substrate, a metal layer on one surface of the isolation substrate, a power loop substrate on the metal layer, an upper switch on the power loop substrate, a lower switch on the power loop substrate and coupled to the upper switch, a capacitor on the power loop substrate and coupled to the upper switch, a first via through the power loop substrate and coupled between the lower switch and the metal layer, and a second via through the power loop substrate and coupled between the capacitor and the metal layer, wherein the power loop substrate has a height and separates the metal layer from the upper switch, lower switch and capacitor by the height.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: HRL Laboratories, LLC
    Inventors: Brian Hughes, Karim S. Boutros, Daniel M. Zehnder, Sameh G. Khalil, Rongming Chu
  • Publication number: 20150116023
    Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.
    Type: Application
    Filed: January 6, 2015
    Publication date: April 30, 2015
    Applicant: FERFICS LIMITED
    Inventors: JOHN KEANE, IAN O'REGAN
  • Patent number: 9007101
    Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventor: Ni Zeng
  • Patent number: 8969914
    Abstract: An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sreenivasa Chalamala, Matthias Baer
  • Patent number: 8970281
    Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 3, 2015
    Assignee: DENSO CORPORATION
    Inventors: Teppei Kawamoto, Yasutaka Senda, Ryotaro Miura
  • Patent number: 8963619
    Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Corporation
    Inventor: Po-Chih Wang
  • Publication number: 20150035580
    Abstract: A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.
    Type: Application
    Filed: July 22, 2014
    Publication date: February 5, 2015
    Inventor: Edoardo BOTTI
  • Patent number: 8928363
    Abstract: The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Ayumu Hatanaka, Kaoru Kato, Katsumi Ishikawa, Naoki Maru
  • Publication number: 20140375375
    Abstract: A controller for a converter is designed to receive from a measuring device measurement signals from an output line of the converter, and to analyze the measurement signals in order to generate a switching signal that has a switching frequency, wherein the controller comprises a sampler for generating a sample signal by sampling received measurement signals. The sampler is designed to perform the sampling at a sampling frequency that is less than three times the switching frequency. A converter comprises a controller in accordance with the invention.
    Type: Application
    Filed: November 27, 2012
    Publication date: December 25, 2014
    Inventors: Janko Horvat, Stefan Laimgruber
  • Patent number: 8884682
    Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Nakahara, Sakae Nakajima
  • Patent number: 8884650
    Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Takahito Miyazaki
  • Publication number: 20140320193
    Abstract: A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region.
    Type: Application
    Filed: August 29, 2013
    Publication date: October 30, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hidetoshi ASAHARA
  • Publication number: 20140312956
    Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.
    Type: Application
    Filed: May 2, 2014
    Publication date: October 23, 2014
    Applicant: ARM Limited
    Inventors: Betina HOLD, Brian CLINE, George LATTIMORE
  • Patent number: 8847663
    Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Shuichi Nagai, Takeshi Fukuda
  • Publication number: 20140240024
    Abstract: A method and apparatus for predictive switching an output have been disclosed.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Inventor: Ingolf Frank
  • Publication number: 20140231624
    Abstract: There is provided a semiconductor integrated circuit including at least one MOS transistor a source or drain of which is connected an output terminal, and a driver circuit configured to drive a back gate or a well of the MOS transistor in a manner that voltage swing is in a same phase as the output terminal.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 21, 2014
    Applicant: Sony Corporation
    Inventors: Tatsuo Shimizu, Seiji Wada
  • Patent number: 8786309
    Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 22, 2014
    Assignee: Apple Inc.
    Inventors: Toshinari Takayanagi, Shingo Suzuki
  • Patent number: 8786360
    Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics Asia Pacific PTE, Ltd.
    Inventor: Justin Ang
  • Publication number: 20140184302
    Abstract: A high frequency switch device includes a branch transmission line corresponding to each output terminal provided with a switching part. In the branch transmission line, the switching part includes a transmission side diode provided in such a manner that a cathode thereof is arranged on a side of an input terminal 41 and an anode thereof is arranged on a side of the output terminal, and a ground side diode provided in such a manner that a cathode thereof is grounded and an anode thereof is electrically connected between the output terminal and the transmission side diode in the branch transmission line. The branch transmission line includes a first capacitor and a second capacitor on the side of the output terminal from the transmission side diode in such a manner that the anode of the ground side diode is connected between the first capacitor and the second capacitor.
    Type: Application
    Filed: May 23, 2012
    Publication date: July 3, 2014
    Applicant: IMAGINEERING, INC.
    Inventors: Minoru Makita, Yuji Ikeda
  • Patent number: 8766702
    Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: July 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Khalid Hassan Hussein, Toshiyuki Kumagai, Shoji Saito
  • Publication number: 20140152373
    Abstract: Power modules with reduced parasitic inductances are provided. A power module includes a first substrate including a first electrically-conductive layer and a second substrate including a second electrically-conductive layer. These substrates may be stacked on each other. A scalable network of power switches may be arranged on the substrates. Power bars may be connectable to the electrically-conductive layers through electromechanical interfaces at selectable interface locations. The locations and/or type of interface may be selectable based on the arrangement of the switches. The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the electrically-conductive layers.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 5, 2014
    Applicant: LOCKHEED MARTIN CORPORATION
    Inventors: Gregory George Romas, JR., David L. Hoelscher, Thomas Eugene Byrd
  • Patent number: 8698547
    Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Nakao
  • Publication number: 20140055171
    Abstract: A driver circuit has a detector circuit including a high side detection transistor, a resistor, and a low side detection transistor connected to a high side output transistor and a low side output transistor. A clamping circuit converts a high voltage amplitude change signal generated at a connection point of the high side detection transistor and resistor to a signal clamped to a voltage range applied on the low side. An OR circuit outputs a signal taking the logical sum of an inverted control signal and an output of a low side first stage drive circuit. A level shifter circuit outputs a level-shifted signal of the OR circuit to a high side first stage drive circuit. A second OR circuit outputs a signal wherein the logical sum of an output signal of the clamping circuit and the control signal is inverted to the low side first stage drive circuit.
    Type: Application
    Filed: February 14, 2013
    Publication date: February 27, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Fuji Electric Co., Ltd.
  • Patent number: 8638129
    Abstract: A power circuit. One embodiment provides a circuit for driving a power transistor having a control electrode and a load path. The circuit includes a driver circuit configured to change the power transistor to a completely on or off state with the aid of a control signal supplied to the control electrode. A series circuit includes a semiconductor switching element and a capacitor. The series circuit is connected in parallel with the load path and the capacitor provides a supply voltage for the driver circuit.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Peter Kanschat, Uwe Jansen, Gerald Deboy
  • Patent number: 8633755
    Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 21, 2014
    Assignee: DENSO CORPORATION
    Inventors: Teppei Kawamoto, Ryotaro Miura
  • Patent number: 8629709
    Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: January 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoyuki Iraha, Tatsuhiko Maruyama
  • Publication number: 20140009202
    Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.
    Type: Application
    Filed: January 23, 2013
    Publication date: January 9, 2014
    Applicant: Panasonic Corporation
    Inventors: Shuichi Nagai, Takeshi Fukuda
  • Publication number: 20130342261
    Abstract: A fast bias circuit including a bias unit, a resistor, a first switch, and a detecting circuit is provided. The resistor has a first terminal coupled to the bias unit to receive a bias voltage, and a second terminal coupled to a bias terminal of a target circuit, wherein the bias terminal is coupled to an input signal. The first switch has a first terminal coupled to the first terminal of the resistor, a second terminal coupled to the second terminal of the resistor, and a control terminal coupled to the detecting circuit. During an initialisation period, the detecting circuit compares the bias voltage with a voltage at the bias terminal of the target circuit to obtain a comparison result, and controls the first switch according to the comparison result. Furthermore, a fast bias method and a bias and load circuit are also provided.
    Type: Application
    Filed: October 11, 2012
    Publication date: December 26, 2013
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventor: Ying-Chung Chiu
  • Publication number: 20130335133
    Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.
    Type: Application
    Filed: August 21, 2013
    Publication date: December 19, 2013
    Applicant: Apple Inc.
    Inventors: Toshinari Takayanagi, Shingo Suzuki
  • Patent number: 8610485
    Abstract: A gate drive circuit includes a turn-on circuit having an upper limiter for receiving a gate drive signal. The upper limiter has an output terminal. The turn-on circuit also has a transistor having a base connected to the output terminal of the upper limiter. In addition, the terminal has a terminal connected to a gate of a power switching device. The upper limiter limits a voltage input to the base of the transistor to not exceed a first predetermined value.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuaki Hiyama
  • Publication number: 20130257510
    Abstract: A high frequency switch circuit including: a first rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a first MOSFET circuit and a first control terminal and the other end connected to ground, and a second rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a second MOSFET circuit and a second control terminal and the other end connected to ground. The circuit further includes a connecting section connecting the forward-current input terminal side of at least one of the rectifier elements of the first rectifier circuit and one of the main terminal sides of the first MOSFET circuit, and connecting the forward-current input terminal side of at least one of the rectifier elements of the second rectifier circuit and one of the main terminal sides of the second MOSFET circuit.
    Type: Application
    Filed: March 8, 2013
    Publication date: October 3, 2013
    Inventors: Hidefumi SUZAKI, Takahito MIYAZAKI
  • Patent number: 8547156
    Abstract: Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus can include a field effect transistor (FET), averaging resistors and a bidirectional current source. The averaging resistors can apply an average of a voltage at the source of the FET and a voltage at the drain of the FET to the gate of the field effect transistor. The bidirectional current source can turn the FET on and off. The FET can operate in the ohmic region when on. Such an apparatus can improve the linearity of the FET as a resistor, for example, at lower frequencies near or at direct current (DC). In some implementations, the apparatus can include one or more current sources to remove an offset introduced by the bidirectional current source at the source and/or the drain of the FET.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: October 1, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Omid Foroudi