Abstract: A device in an emitter-switching configuration comprises a high-voltage transistor having a first terminal connected directly to a first power terminal of the device, a control terminal connected to a control terminal of the device, and a second terminal. The device also includes a low-voltage transistor having a first terminal connected directly to the second terminal of the high-voltage transistor and a second terminal and a control terminal which are connected directly to a second power terminal and to the control terminal of the device, respectively. A circuit portion is provided for recovering an electrical charge discharged from the control terminal of the high-voltage transistor to the second terminal of the low-voltage transistor during the turning-off of the device.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A level shift circuit for receiving an input signal with a first level and a second level that is lower than the first level, and supplying an output signal with a third level and a fourth level, the third level being equal to or higher than the first level, the fourth level being equal to or lower than the second level comprises a high level power supply for supplying a voltage with the third level, a low level power supply for supplying a voltage with the fourth level, an inverter circuit whose input terminal is connected to a supply line of the input signal, a first transistor for connecting an output node thereof to the high level power supply when the output level of the inverter circuit substantially becomes the second level or below, a second transistor for connecting an output node thereof to the low level power supply when the output level of the inverter circuit substantially becomes the first level or above, a third transistor for causing the first transistor to be kept in an non-conductive state w

Abstract: Disclosed is an integrated circuit comprising storage circuits, these circuits themselves comprising insulation transistors to which a determined positive bias voltage may be applied. This bias voltage is determined by means of a first bias circuit. The disclosed circuit comprises a second bias circuit whose time constant in response to a voltage step is smaller than the time constant of the first circuit in response to the same step, this second circuit making it possible to reduce the response time of the first bias circuit.

Abstract: A control circuit for providing fast turn on of a PNP transistor in which a capacitor charging current is boosted and provided to the base of the PNP transistor. An embodiment of the invention provides a current amplifier in parallel with a current source for coupling to the base of the PNP transistor. The PNP transistor is connected to a positive voltage supply. A capacitor is also coupled to the positive voltage supply for delivering a charging current amplifier. In a further embodiment, an NPN transistor has its base coupled to the capacitor and its collector coupled to the base of the PNP transistor for providing the drive current boost. A diode may be coupled to the capacitor for passing a discharge current to the capacitor when the PNP transistor is off and to block the capacitor current when the PNP transistor is being switched on. A PNP drive transistor may be coupled between the collector of the NPN transistor and the base of the PNP transistor.

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

Abstract: The present invention teaches a variety of electrical devices and methods for connecting a switch such as a transistor to decrease a voltage drop across an electrical coupling connecting the switch's source with a gate driver regulating operation of the switch, the voltage drop due, at least in part, to a change in current flowing through the switch. Decreasing the voltage drop from the switch's source to the gate driver tends to improve the operational characteristics of the switch. One embodiment of the present invention teaches an electronic device including a switch having a gate, a drain, and a source, and a plurality of source terminals. A gate bias voltage V.sub.gs (the voltage potential from the gate to the source) controls a flow of current through the switch between the drain and the source. The source terminals are each connected to the source by a distinct electrical coupling, each of the electrical couplings having some inductance.

Abstract: A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

Abstract: A current slew rate limiter for limiting the rate at which current is applied to the base of an NPN output transistor. Current is applied to the output transistor base via a first output port of a current splitter. The current provided by the second output port of the current splitter is fed back to the input of the current splitter via an NPN current mirror and a PNP current mirror connected in series. A current limiting resistor is provided in at least one of the input and output circuits of the PNP current mirror to limit the maximum output current to the base of the NPN output transistor.

Abstract: In one aspect of the present invention a gate drive circuit is disclosed. The gate drive circuit includes a high voltage and low voltage energy source, a power transistor, a switching transistor, and a charging capacitor. The charging capacitor stores energy from the low voltage energy source. The gate drive circuit further includes a circuit that biases the switching transistor OFF which causes the low voltage energy stored in the capacitor to bias the power transistor ON to transfer high voltage energy to the load. The circuit additionally biases the switching transistor ON which biases the power transistor OFF to block the transfer of high voltage energy. Finally, a protection device is included to limit the power transistor voltage to a maximum voltage level in response to the power transistor being biased ON.

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: A pull-up circuit including an NPN bipolar transistor, a P-MOS transistor connected in parallel with the bipolar transistor, a first CMOS inverter for receiving an input signal and controlling the P-MOS transistor, and a second CMOS inverter for receiving the output of the first inverter and controlling the bipolar transistor. An output stage includes the pull-up circuit and also includes a pull-down circuit comprising an N-MOS transistor, a second NPN bipolar transistor connected in parallel with the N-MOS transistor, a control circuit for switching on the second NPN bipolar transistor, and a third inverter whose input is connected to the output terminal and whose output controls the N-MOS transistor and provides a signal to the control circuit for switching off the second NPN bipolar transistor.

Abstract: According to the present invention, schottky diode technology is used to limit the amount of stored charge which must be overcome by an RF transistor during the portion of an RF cycle when the RF transistor attempts to turn on. Limiting the amount of stored charge stabilizes the bias point of the RF transistor on its load line so that the mode of operation of the RF transistor may be maintained. Thus, a schottky diode is placed in a RF transistor circuit and acts as a current sink to bleed stored charge to ground. Placement of the schottky diode close to the RF transistor provides a number of benefits, including introduction of the schottky diode at a low impedance point of the RF transistor circuit, minimization of lead/lag phase angles introduced by intervening matching elements, and minimization of resonance effects.

Abstract: A GTL phased-output driver is provided which employs a pre-driver, a set of phasing elements or delay elements, and a set of output transistors. The pre-driver includes pull up devices, such as PMOS devices, and pull down devices, such as NMOS devices. The PMOS devices of the pre-driver are configured to route output transistor-triggering signals through the phasing elements in one direction whereas the NMOS devices are configured to route output transistor-releasing signals through the phasing devices in an opposite direction. Output transistors of differing sizes are employed. During a pull down operation, controlled by the PMOS pre-driver transistors, the output transistors are triggered sequentially in order from smallest to largest. During a pull up phase, controlled by the NMOS pre-driver transistors, the output transistors are released in a reverse order from largest to smallest. Hence, the largest transistor is triggered first during a pull down phase but is released last during a pull up phase.

Abstract: A radio receiver (40) for receiving an RF signal comprises receiving circuitry (42) for receiving and demodulating the RF signal and a microcomputer (44) coupled to the receiving circuitry (42) for enabling and disabling the receiving circuitry (42) at predetermined times. The radio receiver (40) further comprises an expansion chip (68) coupled to and controlled by the microcomputer (44) for communicating therewith to further process the RF signal. Communication between the microcomputer (44) and the expansion chip (68) occurs at a first speed when the receiving circuitry (42) is enabled and at a second speed faster than the first speed when the receiving circuitry (42) is disabled.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.