Abstract: Certain aspects of the present disclosure provide an apparatus for noise cancellation. One example apparatus generally includes a first delay path and a second delay path, each providing signals generated by applying a different delay to an input signal, and a first comparator having a first input coupled to the first delay path and a second input coupled to the second delay path. The apparatus also includes a switching circuit having a control input coupled to an output of the first comparator, the switching circuit configured to selectively couple the first delay path or the second delay path to an output node of the switching circuit based on a signal at the control input. The apparatus also includes an attenuation circuit having a first input coupled to an input path for providing the input signal, and a second input coupled to the output node of the switching circuit.

Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A method for integrating signals transmitted from a transmitter to at least one ultra wide band receiver, includes initializing a measurement by estimating an initial clock drift ?DHinit between said transmitter and said at least one ultra wide band receiver, thereby generating an estimated clock drift, executing an iterative loop, wherein executing said iterative loop comprises integrating at least one received primary signal, said at least one received primary signal composed of at least two samples, wherein integrating said at least one received primary signal comprises a first integration, and at least one of a second integration and a third integration, wherein said first integration uses said estimated clock drift, said second integration uses said estimated clock drift increased by a predetermined value, and said third integration uses said estimated clock drift decreased by a predetermined value, and selecting from among said integrations an integration that maximizes a quality criterion.

Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.

Abstract: The invention includes a method for transmitting and detecting high speed Ultra Wideband pulses across a wireless interface. The transmitter includes a serializer and pulse generator. The receiver comprises a fixed delay line, multiplier, local serializer (with a sequence matching the transmitter), digital delay lines, low noise amplifier and logic fan-out buffer along with an array of D flip-flop pairs. Each flip-flop pair is enabled, at fixed time increments, to detect signals at a precise time; the timing is controlled by the pseudo-random sequence generated by the local serializer. A local tunable oscillator is controlled by detecting the phase change of the incoming signal and applying compensation to maintain the phase alignment and clock synchronization of the receiver to the clock reference of the transmitter. The invention uses a pair of pulses with a fixed delay and then relies on mixing the two to provide better noise immunity.

Abstract: Provided are transmitter topology, receiver topology and methods for generating and transmitting a radio signal at a transmitter and detecting and processing a radio signal at a receiver. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a transmitter domain (e.g., clock CLK_D1) as input data for the first flip-flop. The clock CLK_D2 through a delay cell also triggers a second flip-flop having the same clock CLK_D1 as input data for the second flip-flop. Based on the output of the first flip-flop (e.g., output S1) and of the second flip-flop (e.g., output S2), the embodiments determine whether the rising and or falling edge of clock CLK_D2 should be used for triggering in a transmitting and receiving application. The embodiments are applicable in both situations where the rising edge or falling edge of clock CLK_D1 is used as a triggering edge. Other embodiments are also disclosed.

Abstract: A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.

Abstract: Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.

Abstract: A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: An address transition detecting circuit comprising a first address transition detecting stage for generating a first address transition detection signal, the first address transition detection signal having a pulse width which is constant and stable when a supply voltage is relatively low, a second address transition detecting stage for generating a second address transition detection signal, the second address transition detection signal having the same pulse width as that of the first address transition detection signal from the first address transition detecting stage when the supply voltage is relatively high, a switching stage for switching selectively the first and second address transition detection signals from the first and second address transition detecting stages to an output line, and a supply voltage detecting stage for detecting a level of the supply voltage and controlling the switching stage in accordance with the detected level.

Abstract: A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

Abstract: A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

Abstract: A pulse width discriminating circuit comprises an edge detecting circuit receiving an input signal for generating a detection signal when the input signal rises up, first to third counters each cleared by the detection signal and counting a different count clock, a capture register responding to the detection signal to store a count value of the first counter, an arithmetic operation circuit for multiplying the stored value in the capture register with a predetermined constant number, and a compare register storing the result of the multiplication operation performed in the arithmetic operation circuit. First to third comparators are provided each comparing the stored value of the compare register with a count value of a corresponding one counter of the first to third counters for generating a coincidence signal, and each of a plurality of latch circuits responds to the coincidence signal of a corresponding comparator of the first to third comparators to latch a level of the input signal.

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.