Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A system for controlling at least one electronic detonator generates, as output, an output power supply signal intended to power the at least one electronic detonator and generating commands to fire the at least one electronic detonator, the control system including a control module configured to generate firing commands and to generate a first power supply signal. The control system further includes a power supply module generating a second power supply signal intended to power the at least one electronic detonator, the output power supply signal corresponding to the second power supply signal once a command to fire the at least one electronic detonator has been generated, and corresponding to the first power supply signal as long as no firing command has been generated.

Abstract: A gate drive circuit for applying a voltage to a gate of a semiconductor switching device is disclosed. The gate drive circuit includes a gate drive controller that provides voltage commands for operating the semiconductor switching device, a plurality of primary gate resistors coupled between the gate drive controller and the semiconductor switching device, one or more secondary gate resistors connected in parallel with the primary gate resistors, a primary transistor connected in series with each of the primary gate resistors, and a secondary transistor connected in series with each of the secondary gate resistors. Further, one of the primary or secondary transistors receives the one or more voltage commands from the gate drive controller and provides one or more corresponding voltage levels to the semiconductor switching device via one of the primary or secondary gate resistors so as to control the on-off behavior of the semiconductor switching device.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.

Abstract: Audio data transmission and reception methods and an electronic apparatus using the same are provided. The audio data transmission and reception methods send audio data by one bit at the rising edge and at the falling edge of a bit clock, and send audio data over a null interval carrying no data. Hence, 5.1 channel audio data can be transmitted and received using an I2S transmission scheme.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop.

Abstract: A high-power switching module for directly feeding pulse energy to a load includes a plurality of series-connected switching stages. Each switching stage includes a semiconductor switch; a snubber capacitor and a synchronizing resistor; and a control network configured to act on the semiconductor switch and to be supplied with auxiliary power and switching pulses from a pulse driver so as to influence a switching of the semiconductor switch. The control network includes at least one control resistor, a control diode, an auxiliary diode, an auxiliary capacitor configured to decouple and store the auxiliary power so as to maintain an offset voltage at the semiconductor switch, and an adjustable time-delay element series connected to the control diode and connected in parallel with the control resistor. The adjustable time-delay element is configured to variably set the offset voltage for the semiconductor switch that determines the switching of the semiconductor switch.

Abstract: A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2?k?N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1?i?N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

Abstract: The disclosure provides a method for reducing an amount of simultaneous switching outputs (SSO) of a device. The method of reducing the amount of simultaneous switching outputs can include driving outputs of the device to a first set of values, scrambling a second set of values to reduce an amount of simultaneous switching outputs resulting from the switching of the first to the second set of values, and driving the outputs of the device to the scrambled second set of values. Further, the method can include descrambling the scrambled second set of values back to the second set of values.

Abstract: An integrated circuit includes a functional circuit module operating at a voltage range between a first voltage level and a second voltage level lower than the first voltage level. A power supply switch module, coupled between the functional circuit module and one or more power supplies, is controlled by one or more controlling biases of voltage levels outside the voltage range between the first and second voltage levels for more fully turning on and off the power supply switch module than biases that are within the range between the first and second voltage levels do.

Abstract: A PWM inverter in which high-surge voltage is not applied across terminals of a switching device thereof is provided by preventing multi-phase simultaneous switching.

Abstract: An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit.

Abstract: The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

Abstract: A method and structure for control of a rise time of a bus signal coupled to a driver circuit. A bus is coupled to the driver circuit and is operable to carry the bus signal. Voltage control elements are coupled to the driver circuit and the bus, and are operable to increase or decrease a voltage of the bus signal relative to a ground at one or more time instants. A control circuit coupled to the voltage control elements is operable to control the switching of the voltage control elements, thereby controlling the voltage level of the bus signal. Controlling a rise time of the bus signal of the driver circuit includes adaptively adjusting a voltage level of the bus signal relative to a ground at one or more discrete times by the use of the voltage control elements.

Abstract: A solenoid control circuit that includes two switching networks that are selectively opened and closed in a current limit cycle to control the magnitude of the current flowing through the solenoid. The configuration of the switching networks is such that current flows through an energy dissipating resistor only when the solenoid is commanded off by the solenoid control circuit, and not during the current limit cycle. Thus, the energy dissipated by this resistor is reduced relative to other solenoid control circuits, making it more efficient, and reducing EMI emissions from the circuit while providing for a fast solenoid response.

Abstract: A bidirectional battery disconnect switch, i.e., a switch which is capable of blocking a voltage in either direction when open and conducting a current in either direction when closed, is disclosed. The switch includes a four-terminal MOSFET having no source/body short and circuitry for assuring that the body is shorted to whichever of the source/drain terminals of the MOSFET is biased at a lower voltage.

Abstract: A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trailing edge of a control input signal, which is detected by the edge detection circuit. The status hold circuit drives an output element in response to the ON pulse outputted from the ON pulse generation circuit and holds driving status of the output element until a first OFF pulse is outputted from the first OFF pulse generation circuit. The second OFF pulse generation circuit generates a second OFF pulse in response to a protect operation signal and supplies this pulse to the status hold circuit, thereby to stop driving of the output element.

Abstract: The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.

Abstract: In a switching arrangement for applying a pulse to a load, for example a magnetron, a plurality of FET modules are stacked along the longitudinal axis and surrounded by a housing enclosing four capacitors. The capacitor means provides a current return path for current applied via the FET switches of the modules the coaxial current cancelling construction of the arrangement results in low circuiting conductance. The capacitance may be sufficiently large to provide electrostatic screening.

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

Abstract: A clock signal control circuit that permits the on-chip circuit dimensional size to be reduced is provided. The clock signal control circuit includes a plurality of amplifier circuit elements amplifying the input clock signal and a plurality of switching elements switching the passage of the clock signal on and off, wherein the plurality of amplifier circuit elements and the plurality of switching elements are connected in such a way that the amplifier circuit elements may be connected in a series fashion when they are operational. Selecting those switching elements that are switched on causes the amplifier circuit elements to be switched so that their series-fashion connection can be reversed to allow the clock signal to travel in the backward direction.

Abstract: Ground bounce and power supply bounce are reduced in an output driver by utilizing a plurality of p-channel and n-channel transistors which are connected to an output pad, by sequentially turning off the p-channel transistors before sequentially turning on the n-channel transistors, and by sequentially turning off the n-channel transistors before sequentially turning on the p-channel transistors.

Abstract: An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.

Abstract: An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

Abstract: A reference voltage generating method and circuit is disclosed where the output can be programmably calibrated for minimum temperature drift. Output calibration is performed by adjusting a value of resistance of a resistor in a band-gap circuit. Digitally programmable switches are used to incrementally reduce or increase the value of the target resistor. The control circuit according to the present invention is also designed such that it tracks variations in process and temperature.

Abstract: A circuit arrangement for limiting the current to be switched of an electrical load, with the power input of the electrical load being controlled by means of a Triac, said Triac being connected in series with the electrical load, with a Diac being connected to the gate terminal of the Triac, said Diac being connected in series with a resistor arrangement whose resistance value is variable for the purpose of controlling the Triac, said Triac being disconnectible from the power supply by means of a first switch, wherein a second switch is provided by means of which the series arrangement comprised of the resistor arrangement and the Diac is disconnectible from the power supply, and wherein, on turning the electrical load on, the first switch is closed first, while the second switch is closed with a time delay. Advantageously, on turning the electrical load off, the second switch is opened first, while opening of the first switch occurs with a time delay.

Abstract: In a GTL circuit for restraining a ringing occurred by parasitic active elements on a package and a transmission path, the GTL circuits comprises two NMOS transistors connected in series to each other, for restraining a ringing between the gate and drain of an open drain type NMOS transistor which drives an output potential, and a plurality of delay circuits connected in series, for controlling periodically a current flowing through the two NMOS transistors, thereby reducing the ringing exceedingly the ringing caused by extremely large inductive elements which are connected to an output terminal as loads, and achieving a high speed operation of the GTL circuit.

Abstract: This application discloses circuit and method for reducing the turn-off time of a power transistor driving an inductive load. The circuit clamps the gate to source of a power transistor by using two field effect transistors as the current path across the gate and source of the power transistor. A zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection.

Abstract: A pulse counter circuit has an invertor which inverts a pulse signal input thereto to form an inverted signal. One of the pulse signal and the inverted signal is selected in response to a selecting signal, and the selected signal is delivered as an output signal. Changeover of a signal to be selected between the pulse signal and the inverted signal is effected at timing of a change in level of the pulse signal. A counter counts pulses of the output signal. A pulse signal changeover circuit selects one of a pulse signal and an inverted signal obtained by inverting the pulse signal, in response to a selecting signal, and the selected signal is delivered as an output signal. The pulse signal is masked by being held at a predetermined level within a predetermined time period, and the inverted signal is masked by being held at the predetermined level within the predetermined time period.

Abstract: A variable delay line having a string of "slow" logic inverters and an equal number of "fast" inverters with inputs connected to corresponding "slow" inverter inputs. Transmission gates, coupling the "fast" inverter outputs to corresponding "slow" inverter outputs, vary the amount of current from the "fast" inverters added to the output current of the corresponding "slow" inverters. Maximum delay occurs when substantially no current from the "fast" inverter is added to the "slow" inverter output current and minimum delay occurs when substantially all the current from the "fast" inverter is added to the "slow" inverter output current. The variable delay line may be configured into a variable frequency ring oscillator, useful in phase-locked-loops or the like.

Abstract: A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.