Abstract: A motor control method for coupled an electronic vehicle is provided. The motor controller controls a motor and is powered by a battery. The motor control method includes: when a main relay of the motor controller suddenly breaks contact, in a first phase, feeding back a surge current into the battery to suppress the surge current by a diode and a first current limit resistor of a first protecting circuit of the motor controller; and, in a second phase, conducting a discharge switch of a second protecting circuit of the motor controller by a control unit of the motor controller, and releasing the surge current to a reference voltage range by the discharge switch and a second current limit resistor of the second protecting circuit.

Abstract: An electric circuit for testing a power-on reset circuit. The electric circuit including a comparator, which is configured to detect an undervoltage for an input voltage to be compared to a reference voltage and to output an output signal, a first noise filter for filtering out noise from the output signal received as a first input signal for a first time period and for outputting a first filtered output signal of a second noise filter for filtering out noise from a second input signal for a second time period, and for outputting a second filtered output signal, and a digital part having an OR gate for the logical linkage of a first filtered output signal and a second filtered output signal for the output of a power-on reset signal.

Abstract: The present disclosure includes a drive circuit (2-4) for switching a switching element, and a variable capacity circuit (6A), connected between a control terminal (G) of the switching element and the drive circuit (2-4), capable of switching at least between a first capacity value and a second capacity value different from the first capacity value, and controls a capacity value between the control terminal and the drive circuit via the variable capacity circuit.

Abstract: An interactive system based on light ray intensity recognition includes a smart device and a toy. The smart device has a touch control display screen providing variable brightness display. The toy is fitted onto the touch control screen and a light ray detection circuit is mounted on the bottom of the toy. The toy includes an LED drive circuit and an electromagnetic coil drive circuit; the output of the light ray detection circuit is respectively connected to an input of the LED drive circuit and an input of the electromagnetic coil drive circuit, the light ray detection circuit implementing detection of a brightness signal of the display picture of the touch control display screen of the smart device and outputting a drive signal, such that the LED drive circuit drives an LED to light up, switch off, or flash, and the electromagnetic coil drive circuit drives the toy to vibrate.

Abstract: A synchronizing high-speed clock divider has a Clk input, a Clks input, and a reset input configured to correct phase misalignment on clock divider outputs caused by phase skew between a Clk input signal and a Clks input signal, and comprises a reset synchronizer configured to generate at least one synchronous internal reset signal in response to a reset signal and the Clk input signal, a first clock divider configured to receive the Clk input signal on the Clk input and a reset signal on a first clock divider reset input to provide a Clk out signal, a second clock divider configured to receive the Clks input signal on the Clks input and the reset signal on a second clock divider reset input to provide a Clks out signal, a phase skew detector configured to detect a phase alignment between the Clk out signal and the Clks out signal, and a phase skew corrector coupled to the phase skew detector and the second clock divider configured to change the phase alignment to be within a same phase as the first clock div

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.

Abstract: A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “?15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (?15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “?15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: A circuit includes a delay circuit, a transition detector, a pre-driver circuit, and a controller. The delay circuit includes an input for receiving a signal and an output for providing a delayed version of the signal. The transition detector is coupled to the input of the delay circuit to detect a transition within the signal and to provide a look ahead signal to a detector output. The pre-driver circuit includes an input coupled to the output of the delay circuit, a control input, at least one signal output, and a plurality of a bias outputs. The controller is coupled to the detector output and to the control input of the pre-driver circuit and is configured to control bias signals on a plurality of bias outputs to selectively increase a driving strength of signals and biases applied to an output stage in response to the look ahead signal.

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch.

Abstract: Under-voltage, over-voltage, and temperature detectors disposed in a switching circuit are turned on periodically and in response to an oscillating signal having a low duty cycle. Accordingly, because the voltage and temperature detectors remain off for long durations, their operating currents, and thus the operating current of the switching circuit is substantially reduced. The switching circuit has a current limiting function which is disabled when the switch current is below a threshold value, thereby further decreasing the current consumption of the switching circuit at low switch current levels.

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract: An inverter control apparatus is provided that offers a ‘soft turn off’ to a gate operation of the inverter so as to securely protect the IGBT. In particular, an inverter control system according to the present invention may include a gate operating portion that controls turn on/off of an IGBT and forcibly turns off the IGBT if a short circuit or an over current is detected from the IGBT, a current buffer that amplifies a control current for the turn on/off of the IGBT that is outputted from the gate operating portion, and a filter that delays the forcible turn off control current that is outputted from the gate operating portion.

Abstract: A circuit includes a delay circuit, a transition detector, a pre-driver circuit, and a controller. The delay circuit includes an input for receiving a signal and an output for providing a delayed version of the signal. The transition detector is coupled to the input of the delay circuit to detect a transition within the signal and to provide a look ahead signal to a detector output. The pre-driver circuit includes an input coupled to the output of the delay circuit, a control input, at least one signal output, and a plurality of a bias outputs. The controller is coupled to the detector output and to the control input of the pre-driver circuit and is configured to control bias signals on a plurality of bias outputs to selectively increase a driving strength of signals and biases applied to an output stage in response to the look ahead signal.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: Semiconductor relays switch power supplied from a power source to drive loads, and further detect current values of electric currents flowing through the loads. A control section intermittently turns ON the semiconductor relays via driving circuits, thereby limiting electric power consumption of the loads. Further, the control section calculates, based on the current values detected by the semiconductor relays, load electric power consumption of the loads, and estimated electric power consumption of the loads when the semiconductor relays are continuously ON, and allows a display section to display, as a value indicative of an energy-saving effect, an electric power amount difference i.e. a saved electric energy that is based on an electric power difference obtained by subtracting the load electric power consumption from the estimated electric power consumption.

Abstract: Capacity degradation due to charge/discharge cycles is suppressed in either a non-aqueous electrolyte secondary cell provided with a positive electrode including, as a positive electrode active material, a lithium-transition metal complex oxide having a layered structure and containing at least Ni and Mn as transition metals, and a negative electrode containing a carbon material as a negative electrode active material and having a higher initial charge-discharge efficiency than that of the positive electrode, or an assembled battery having a plurality of cells each of which is the secondary cell. A control circuit incorporated in the secondary cell or the assembled battery, or in an apparatus using the secondary cell or the assembled battery, monitors the voltage of the secondary cell or each of the cells in the assembled battery so that the end-of-discharge voltage of each cell is 2.9 V or higher.

Abstract: A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

Abstract: An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Abstract: In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch.

Abstract: A network of processing units having at least one switch that allows disruption of the network between a first and a second processing units is provided. Disruption of the network by means of the switch effectively disconnects the first processing unit from the network and couples the first processing unit to a controller of the network. The controller is adapted to exchange data with the disconnected processing unit and thereby allows selective and direct data exchange with a selected processing unit. In particular, in the framework of heterogeneous and hierarchical networks of processing units, the switch techniques provide direct access to processing units and sub-networks and allow for an efficient and fast performance of diagnostic and maintenance procedures of sub-networks and their corresponding processing units, such as performing a flashing procedure.

Abstract: A method comprises initiating generation of a feedback signal in response to determining that an input has been selected throughout a first predetermined period of time and initiating a forced shutdown of a device in response to determining that the input has been deselected within a second predetermined period of time after the initiating of the generation of the feedback signal.

Abstract: An audio reproducing apparatus includes a power supply, an amplifier, a speaker, and a controller. The power supply is for supplying a voltage. The amplifier is for receiving the voltage and audio signals, amplifying the audio signals, and outputting amplified audio signals. The speaker is for reproducing sound after receiving the amplified audio signals. The controller is for receiving the voltage and generating a control signal to enable the amplifier. The controller includes a generator and a delay unit. The generator is for receiving the voltage and generating the control signal. The delay unit is for delaying the time of transferring the voltage from the power supply to the generator.

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract: A circuit for controlling time sequence of an electronic device, the circuit comprises a delay unit to receive a first control signal, a first switch unit connected to the delay unit to receive the first control signal after a rising edge of the first control signal, a second switch unit to promptly receive the first control signal in response to a falling edge of the first control signal, and a voltage output unit connected to the first and second switch units. The voltage output unit is selectively controlled by the first or the second switch unit to output a second or a third control signal to turn on or off the electronic device.

Abstract: In a particular embodiment, an apparatus includes a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.

Abstract: A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.

Abstract: The present invention discloses a timing control apparatus to control the on/off timing of the voltage sources. The timing control apparatus includes a plurality of delay circuits coupling with the voltage sources, a plurality of discharging circuits coupling with the delay circuits and a plurality of switches coupling with the discharging circuits.

Abstract: An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current.

Abstract: A circuit for controlling time sequence of an electronic device, the circuit comprises a delay unit to receive a first control signal, a first switch unit connected to the delay unit to receive the first control signal after a rising edge of the first control signal, a second switch unit to promptly receive the first control signal in response to a falling edge of the first control signal, and a voltage output unit connected to the first and second switch units. The voltage output unit is selectively controlled by the first or the second switch unit to output a second or a third control signal to turn on or off the electronic device.

Abstract: A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.

Abstract: An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.

Abstract: A motor-drive circuit comprising: a current-passage-control circuit to perform ON/OFF control of a drive transistor connected to a motor coil to pass current through the motor coil; an overcurrent-state-detection circuit to detect whether current passing through the drive transistor is in an overcurrent state where the current exceeds a predetermined threshold value; a charging and discharging circuit to start charging a capacitor in response to detecting the overcurrent state by the overcurrent-state-detection circuit and subsequently discharge the capacitor in response to not detecting the overcurrent state; and an overcurrent-protection-control circuit to stop the ON/OFF control to turn off the drive transistor, for an elapsed charging period for a charging voltage of the capacitor at a predetermined voltage to exceed a threshold voltage, and determine whether to perform such an overcurrent-protection-control as to turn off the drive transistor by detection of the overcurrent state, after the charging peri

Abstract: An electric circuit device operable under a power supply includes: a circuit; a first switch connected between the power supply and the circuit; a capacitor tending to produce a first leakage current; a second switch connected between the power supply and the capacitor, the second switch producing a second leakage current when it is cut off, the second leakage current being less than the first leakage current; and a switch controller for turning on the second switch while both the first switch and the second switch are turned off, and after a first time passes for turning on the first switch.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current flowing in the signal wire is amplified toward a voltage to which a potential of the signal wire transits during the potential transition in the signal wire and further controls the gate voltage so that a voltage value obtained after the potential transition in the signal wire is retained after the potential transition in the signal wire.

Abstract: The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.

Abstract: The present invention discloses a timing control apparatus to control the on/off timing of the voltage sources. The timing control apparatus includes a plurality of delay circuits coupling with the voltage sources, a plurality of discharging circuits coupling with the delay circuits and a plurality of switches coupling with the discharge circuits.

Abstract: A gate drive circuit includes a turn-on side circuit for turning on a gate of a power switching device, the turn-on side circuit including a first turn-on side power supply circuit and a second turn-on side power supply circuit, the first turn-on side power supply circuit including: a first turn-on voltage source for supplying a first turn-on voltage; first turn-on wiring; and a first turn-on switch connected in the first turn-on wiring and controlled by a gate drive signal; and the second turn-on side power supply circuit including: a second turn-on voltage source for supplying a second turn-on voltage applied to the gate of the power switching device to set the power switching device in a steady (on) state; second turn-on wiring; a second turn-on switch connected in the second turn-on wiring; and a turn-on side delay circuit for delaying the gate drive signal and passing it to the second turn-on switch.

Abstract: A control terminal is connected to an external resistor, and is connected to a time constant capacitor. A control unit compares a control voltage with a threshold voltage, and switches the function of a semiconductor device according to the comparison results. A charge/discharge circuit charges or discharges the time constant capacitor connected to the control terminal. The semiconductor device uses the voltage at the control terminal, which changes according to the charging operation or the discharging operation performed by the charge/discharge circuit, as a time constant voltage.

Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.

Abstract: A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.

Abstract: A hysteretic DC/DC converter is proposed that operates at a high switching frequency without producing undesired pulse bursts at the output. The converter has a converter power stage with a supply voltage input, a controlled voltage output and an enable input. A comparator has a reference voltage input, a feedback input and an output, and a gating circuit connected between the output of the comparator and the enabling input of the converter power stage. The gating circuit inhibits as a function of load requirements the propagation of enabling pulses from the output of the comparator to the enabling input of the converter power stage. By gating the output of the comparator in a way to separate the output from the enabling input of the converter power stage immediately after the start of each conversion pulse, the generation of further pulses immediately after each conversion pulse is prevented, thereby keeping the output voltage ripple low.

Abstract: A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.

Abstract: A drive circuit includes a gate voltage detector that detects a gate-emitter voltage Vge that appears between the gate and emitter of a power semiconductor device throughout a detection time period during which a sampler allows the process of detecting the gate-emitter voltage Vge, and that recognizes the occurrence of an abnormality in the power semiconductor device when the gate-emitter voltage Vge exceeds a reference value. Therefore, the drive circuit can protect the power semiconductor device with higher reliability by promptly detecting the occurrence of a short circuit even when the power semiconductor device is resistant to high voltages.

Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

Abstract: A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied to the first node based on a delay control signal and generates first to n-th (n is an integer more than 1) internal clock signals. The first internal clock signal is outputted from the second node. Also, the internal clock signals other than the first internal clock signal are outputted from the delay circuit without passing through the second node, and lead the first internal clock signal in phase. The phase comparing circuit compares the original clock signal supplied from the first node and the first internal clock signal supplied from the second node, and outputs a phase difference of the original clock signal and the first internal clock signal. The delay control circuit outputs the delay control signal to the delay circuit based on the phase difference outputted from the phase comparing circuit.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.