Abstract: A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and each forming a NOT-AND (NAND) gate circuit; here several layout units conforming to a first layout pattern are sequentially arranged in a first row of the array; and several layout units conforming to a second layout pattern are sequentially arranged in a second row of the array; here the first layout pattern is different from the second layout pattern, and the first layout pattern and the second layout pattern are such that the first row and the second row form a center-symmetrical structure.

Abstract: A current going through the first power semiconductor is sensed by a first and a second current derivative sensing means, the current going through the second semiconductor is sensed by a third and a fourth current derivative sensing means, when the current going through the first power semiconductor increases, the first current derivative means providing a positive voltage and the second current derivative means providing an opposite negative voltage, when the current going through the second power semiconductor increases, the third current derivative means providing a positive voltage and the fourth current derivative means providing an opposite voltage and the system reduces the voltage on the gate of the first power semiconductor if the first and third current derivative means provide voltages of same sign and reduces the voltage on the gate of the second power semiconductor if the second and fourth current derivative means provide voltages of same sign.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.

Abstract: A driving circuit and a switch signal generation method are provided. The driving circuit receives a PWM signal and provides a first switch signal and a second switch signal. The driving circuit includes a logical signal circuit, a lower bridge dead time circuit and a lower bridge driving circuit. The logical signal circuit provides a first logical signal and a second logical signal according to the PWM signal. The lower bridge dead time circuit determines a leading edge of a lower bridge dead time signal according to the first logical signal and determines a trailing edge of lower bridge dead time signal according to a trailing edge of first switch signal. The lower bridge driving circuit determines a leading edge of second switch signal according to second logical signal and determines a trailing edge of second switch signal according to the trailing edge of lower bridge dead time signal.

Abstract: A transceiver device comprises a transceiver unit including an RF antenna, a serial communication port operatively coupleable with a further corresponding serial communication port of a protection and control device, a serial communication bus electrically connected between said serial communication port and said transceiver unit and having a transmission line and a reception line, a battery unit, and a feeding unit to feed said transceiver unit with a feeding voltage. The feeding unit comprises a first power supply stage electrically connected with said battery unit to harvest electric power from said battery unit and a second power supply stage electrically connected with the transmission line of said serial communication bus to harvest electric power from said transmission line, when said transmission line is said stand-by condition and takes an high-level voltage value.

Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

Abstract: Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) is disclosed. In one aspect, a sensor is placed on each tier of a 3DIC to evaluate a speed characteristic of each tier relative to the speed characteristic of another tier. Based on determining the relative speed characteristics, a control signal may be provided to adjust back body bias elements for clock buffers. Adjusting the back body bias effectively adjusts a threshold voltage of the clock buffers. Adjusting the threshold voltage of the clock buffers has the effect of slowing down or speeding up the clock buffers. For example, slow clock buffers may be sped up by providing a forward body bias and fast clock buffers may be slowed down by providing a reverse body bias. By speeding up slow elements and slowing down fast elements, compensation for the relative speed characteristics may be provided.

Abstract: There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.

Abstract: A circuit comprises a first set of first transistors and a second set of transistors. The first transistors are configured to be turned on in a sequential manner. The second transistors are configured to be turned on in a sequential manner after the first transistors are turned on. A transistor of the first set of first transistors corresponds to a first time delay. The first set of first transistors corresponds to a second time delay that is a multiple of the first time delay.

Abstract: A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock.

Abstract: A control circuit includes a control module, a delay module, and an electronic switch. The control module is connected between a power supply and a load. The delay module is connected to the control module and the electronic switch. A first terminal of the electronic switch is connected to the control module and the delay module. A second terminal of the electronic switch is connected to the power supply. A third terminal of the electronic switch is connected to the load.

Abstract: A control circuit includes a control module, a delay module, and an electronic switch. The control module is connected between a power supply and a load. The delay module is connected to the control module and the electronic switch. A first terminal of the electronic switch is connected to the control module and the delay module. A second terminal of the electronic switch is connected to the power supply. A third terminal of the electronic switch is connected to the load.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

Abstract: A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock.

Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.

Abstract: A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal.

Abstract: A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time.

Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.

Abstract: This documents discusses, among other things, apparatus and methods for a switch circuit including a break-before-make delay and a gradual turn-on. In an example, a switch circuit can include a switch transistor having a control node and coupled to a first node and a second node, a delay circuit configured to receive control information and to provide the control information after a delay interval, and a gradual turn-on circuit configured to receive the delayed control information from the delay circuit and to transition the transistor from the off-state to the on-state over a ramp interval in response to the delayed control information.

Abstract: A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection.

Abstract: A power switch circuit that ensures suppression of an increase in a transient current. The power switch circuit includes a first transistor, which generates an output voltage in response to a control signal, and a time difference generation circuit, which delays the control signal by performing a logical process with the output voltage of the first transistor and the control signal.

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.

Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A clock signal control circuit that permits the on-chip circuit dimensional size to be reduced is provided. The clock signal control circuit includes a plurality of amplifier circuit elements amplifying the input clock signal and a plurality of switching elements switching the passage of the clock signal on and off, wherein the plurality of amplifier circuit elements and the plurality of switching elements are connected in such a way that the amplifier circuit elements may be connected in a series fashion when they are operational. Selecting those switching elements that are switched on causes the amplifier circuit elements to be switched so that their series-fashion connection can be reversed to allow the clock signal to travel in the backward direction.

Abstract: A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract: A power applying circuit for an internal logic circuit includes a plurality of basic power applying units coupled to the internal logic circuit in parallel, each of the basic power applying units including a logic gate unit outputting a pulse in response to two input signals having a time interval with respect to each other, and a transmission gate coupled to the logic gate unit and receiving the pulse.

Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level.

Abstract: A method and an apparatus in testing whether the frequency of an incoming signal is higher or lower than a predetermined value. The method only demands a capacitor (C), a resistor (R), a field effect transistor (Q) and a constant current generator (I). Because the included capacitor only needs to have a small value, a circuit design according to the method is very suitable for integration, for example, in form of a monolithic integrated circuit for frequency control in connection to DC/DC converters.

Abstract: A switching circuit utilizing MOS transistors without body effect having a first transistor inserted with source and drain terminals between two connection terminals, and a second and third transistors inserted in series by means of their respective source and drain terminals between the first transistor and a ground. The gate terminal of the second transistor is connected to the gate terminal of the first transistor to which is applied a command signal. Upon switching a signal is applied in phase opposition to the command signal to the gate terminal of the third transistor. The substrates of the first and the second transistors are connected to a connection node between the second and third transistors. The substrate of the third transistor is connected to ground.

Abstract: Method and apparatus for controlling an output transistor in an output driver circuit. In one embodiment of the invention, an input signal is routed to a first gate body which is disposed over a first channel region in a substrate. The first gate body has a first resistance to the input signal and delays the input signal through the first gate body to provide a delayed input signal. This delayed input signal is routed to a second gate body which is disposed over a second channel region in the substrate. The first gate body is coupled to the second gate body to provide the delayed input signal to the second gate body. According to one embodiment of the invention, the transistor includes the first gate body coupled to an input signal and coupled to the second gate body to receive the input signal through the first resistance of the first gate body.

Abstract: A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

Abstract: An improved power interface device suitable for managing power for a PCMCIA card is disclosed which includes internal charge pumps, to gradually turn on the device's internal N-channel MOSFETs, and a first discharge circuit for gradually turning off the N-channel MOSFETs. The first discharge circuit includes an MOS capacitor that incrementally discharges the gates of the N-channel MOSFETs such that the turn-off speed of each N-channel MOSFET is controlled by the ratio of the capacitances of the capacitor and the MOSFET's gate. A second discharge circuit includes a capacitor and is used to gradually turn on the interface device's internal P-channel MOSFET by incrementally charging its gate. The turn-on speed of the P-channel MOSFET is controlled by the ratio of the capacitances of this capacitor and the MOSFET's gate. In another embodiment, diode clamps are provided to protect the interface device's N-channel MOSFETs against time dependent breakdown.

Abstract: A transistor circuitry keeps its constituent transistors from being forward biased to prevent injection of large currents into the transistor substrates, and like problems. The transistor circuitry achieves this result with a control circuit which generates a substrate control voltage and switching transistors which are prevented from receiving a high constant current voltage from an input terminal until the substrate control voltage is raised up to and held at a desired voltage level.

Abstract: A reset circuit asserts, de-asserts and re-asserts a reset signal in response to a voltage applied between first and second nodes to which the reset circuit is connected. The reset signal includes a plurality of transistor switches connected together with positive feedback to achieve latching of the reset signal in either a high or a low state. The different inherent conductivity characteristics of the transistor switches causes the switches to begin closing when the applied voltage is at a first predetermined level and causes the transistor switches to begin opening when the applied voltage achieves a second predetermined lower level. The conductivity characteristics of the transistor switches cause the first and second predetermined levels to slightly vary over temperatures in the range of approximately -50.degree. C. to 150.degree. C., allowing reliable operation over a wide range of temperatures. The reset circuit may be integrated with the circuit which it resets.

Abstract: An improved Schmitt trigger, especially useful for large scale integrated circuit applications, includes a buffer (inverter) having a pull up device and two pull down devices all connected between a voltage supply and ground, and each receiving the input signal at its gate terminal. A node between the output terminals of the pull down devices is connected to the output terminal of the Schmitt trigger. A feedback line connects the output terminal of the Schmitt trigger to the gate of an N-channel depletion device connected between the pull-up and pull-down devices. Also provided are two devices to control the timing of the Schmitt trigger; these two control devices are connected between the output terminal of the Schmitt trigger and the output terminal of the inverter.Also provided in one embodiment is electrostatic discharge protection connected to the Schmitt trigger input and output terminals, and in another embodiment a control device for turning on and off the supply voltage to the inverter.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Abstract: A slope control circuit having a plurality of resistive elements connected in parallel, each of the resistive elements including a control element for causing the associated resistive elements to be one of electrically conductive or electrically nonconductive, a delay circuit having a plurality of delay components coupled together in series, each of the delay components having a predetermined delay, the junction of each different adjacent pair of the delay components being coupled to the control element of a different one of the resistive elements and a load circuit coupled across the plurality of resistive elements. The circuit can further include a delay adjust circuit for adjusting the delay of each of the delay components, either initially or on-line. The resistance of each of the resistive elements can be the same or different. The plurality of resistive elements and the delay components are all disposed on a single semiconductor chip.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.

Abstract: A control and monitoring circuit for a power switch comprises a first portion (20) connected to this switch and fed with reference to a floating voltage (V.sub.F) of an electrode of this switch, a second portion (10) connected to circuits external to the switch and fed with reference to a fixed voltage, a coder (40) arranged on the side of the second portion and a suitable decoder (50) arranged on the side of the first portion.