Abstract: A pulse width modulator circuit with circuitry for providing a first and second pulse width modulation signal with dead time periods between the first and second pulse width modulation signals, an input for receiving a signal representative of a current in a load adapted to be driven in response to the first and second pulse width modulation signals, and circuitry coupled to the input for adjusting the dead time periods in response to the signal representative of a current.

Abstract: An injector device includes a housing and a cartridge having a reservoir for medicament. The injector device further includes a needle unit comprising a needle, and an actuator. The needle unit is movably mounted to the housing and, prior to use of the injector device the reservoir, is sealed from the needle. The actuator is configured to move the needle unit 5 into engagement with the cartridge such that the needle is moved into fluid communication with the reservoir. A thread is arranged to cause rotation of the needle unit as the needle unit moves into engagement with the cartridge.

Abstract: An image processing apparatus includes a determining section that determines an evaluation period relating to a sync signal according to a processing timing of image information, a signal outputting section that outputs a timing signal in a case where the sync signal is not received in the evaluation period, and a control section that controls the processing timing in accordance with the timing signal.

Abstract: Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

Abstract: An integrated circuit includes circuit blocks, a clock network coupled to the circuit blocks, and a supply voltage network coupled to the circuit blocks. Each of the circuit blocks comprises at least one clocked circuit that receives a clock signal. The clock network provides the clock signal to the clocked circuits in the circuit blocks. The supply voltage network provides a supply voltage to the circuit blocks. A latency of the clock signal provided through the clock network to at least one of the circuit blocks is adjusted to decrease a peak voltage drop in the supply voltage caused by a peak current drawn by the circuit blocks.

Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Abstract: Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Abstract: A detector is provided that detects a detection signal corresponding to a driving vibration, which excites a vibrator in an oscillation loop, and a physical quantity to be measured. The detector includes an amplifying circuit, a synchronous detection circuit, an impedance conversion circuit, a first low pass filter, and a second low pass filter, wherein each of the first and second low pass filters is formed by a switched capacitor filter circuit, a gain of the first low pass filter is different from that of the second low pass filter.

Abstract: In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal.

Abstract: A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: A data output circuit of a semiconductor apparatus includes a clock skew compensation repeater configured to control a delay amount of a clock in response to skew compensation codes and output a data synchronization clock; a mismatch compensation driver configured to synchronize internal data with the data synchronization clock and output the internal data synchronized with the data synchronization clock by controlling a transition timing of the internal data according to mismatch compensation codes; and a data output driver configured to generate output data in response to an output of the mismatch compensation driver.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

Abstract: A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.

Abstract: A detection device includes a detection circuit and a reference voltage supply circuit. The detection circuit includes an amplifier circuit, a synchronous detection circuit, and a filter section. The reference voltage supply circuit includes a first supply circuit which includes a reference-voltage first-type operational amplifier and supplies an analog reference voltage to the amplifier circuit, and a second supply circuit which includes a reference-voltage second-type operational amplifier and supplies the analog reference voltage to the filter section.

Abstract: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2?b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A detection circuit which can reliably detect an out-of-synchronism state of a clock signal with respect to data even if jitter is present in a data signal. A delayed clock signal obtained by delaying a clock signal by 90° through a delay circuit is input to a data input (D) of a flip flop, and the clock signal is read in at the point of change of the data. A logic product of the inverted output of the flip flop and the data signal is obtained by an AND circuit. Then, a logic product output is counted by a counter circuit, and an out-of-synchronism state of the clock with respect to the data is detected based on the output of the counter circuit.

Abstract: An RF band receiver for concurrently monitoring a plurality of contiguous channels within the RF spectrum to unambiguously detect time-coincident signals. The receiver includes a plurality of transmission paths feeding a like number of digital, mixed-base code channels. Each mixed-base code channel includes a harmonic mixer, an IF amp, a plurality of bandpass-filters and a like plurality of detectors. The outputs of the detectors for each mixed-base code channel are fed to a frequency sorter whose output is a digital frequency word which indicates the frequency(s) of the received signal(s).

Abstract: A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.

Abstract: A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_CLOCK state, the sub-unit periodically transmits bursts of clock signals to signal the other sub-unit that it is powered up.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The carrier recovery circuit is constituted such that a phase synchronous circuit constituted by a PLL is controlled by a signal obtained by removing a sign component from an input carrier wave.

Abstract: An apparatus for use in a synchronous transmission system, for detecting a failure of a clock signal, which comprises: a reference clock generator for generating a reference clock signal (RCS) in response to a reset signal issued by a system controller in the STS; and means for receiving a clock signal, the RCS issued by the reference clock signal generating means and the reset signal and for producing a failure signal for the received clock signal, wherein the failure represents a state of a clock in which the clock does not have a pulse for a predetermined time interval, the time interval being measured by using the RCS.

Abstract: A semiconductor integrated circuit, having circuit blocks to be evaluated in AC performance, includes a first circuit for inputting a first signal and a second signal generated in the interior of the semiconductor integrated circuit. The first circuit outputs a transient current when the first signal and the second signal change simultaneously. In the semiconductor integrated circuit, the transient current (third signal) is output to a external terminal of the semiconductor integrated circuit for evaluating the AC performance of the block.

Abstract: An IC testing apparatus has a detecting circuit for detecting an inversion of an output state of a test output from an IC under test in response to application of a clock signal, a comparing circuit for comparing a value preset in a storage circuit with the output state of the test output and an output state of the detecting circuit. In a first comparison operation, the number of pulses of the clock signal applied to the IC under test is less than the number of pulses required to invert the output state of the test output by one pulse and the test output and detector output are compared with corresponding values preset in the storage circuit at times coincident with a test strobe signal synchronized with the clock signal. In a second comparison operation, another clock pulse is applied to the IC under test to make the total number of pulses equal to that needed for inverting the test output and the above comparisons are again made with corresponding preset values.

Abstract: A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted value, large magnitude of frequency departure of repeated frequency of the reference clock from a frequency that should be is judged. Also, through comparison of given number of lower bits of the counted value and externally set detecting value, departure of the repeated frequency of the reference clock from the frequency that should be, is judged. When the counted value reaches a predetermined value, free running condition of the counter is judged to stop counting operation. When judgement is made that the repeated frequency of the reference clock is departed from the frequency that should be, the working reference clock is replaced with a back-up reference clock in response to an alarm.

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.

Abstract: A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck.

Abstract: An inherent-security signal comparator (COMP) is driven by two or more input signals (V1, *V2) coming from a control system (.mu.P1, .mu.P2) and generates an alternate output signal (C) of a predetermined frequency whenever both its input signals are identical and terminates its output signal when its input signals wander off from identity, or any of the circuit components of the comparator break down, or its d.c. supply is interrupted. An amplifier (AMP) driven by the comparator drives an isolating transformer (TR) coupled to a voltage rectifier/regulator device (REG) for the supply to the control system. Preferably an oscillator (OSC), whose output is connected to the input of the amplifier (AMP) in common with the output of the comparator, is supplied by a voltage pulse generated by a monostable circuit (T3-R7-R8-R9-C5-C6-D1-D2) which is momentarily enabled at the start-up of the supply circuit.

Abstract: A delay element (10) generates a delay pulse (OUT) the length of which is not dependent on an available system clock. The delay element uses oscillators (12a, 12b, 12c) and edge detectors (16a, 16b, 16c) to generate a delay based on the beat frequency of the oscillators. The delay element is suitable for fabrication as part of a CMOS integrated circuit, and requires less layout area than alternative methods.

Abstract: A device detecting a sync signal is provided, which comprises a sync signal detector having an output selector, an internal clock generator and a combination of three current mirror circuits formed of MOS transistors, and two MOS transistors having resistance characteristics. Irrespective of the high and low state of the input clock signal, the selecting signal for selecting the received sync signal, is made to be high, and the discharge time of the capacitor is minimized so that a capacitor having small capacity can be used and the volume of an integrated circuit element can be minimized and the stable operation is performed, irrespective of the frequency band of the sync signal and the duty thereof.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting.