By Frequency Patents (Class 327/39)
  • Patent number: 11797965
    Abstract: Wireless communication and proximity-based feedback technologies are disclosed. In some examples, a system identifies that a wireless communication interface has received wireless signal(s) for conveying information from a transaction object in response to proximity between the transaction object and the interface. The system identifies, based on relative signal strength of the signal(s) as received at each of a plurality of antennae of the interface, an indication of a relative position of the transaction object relative to the interface. The system generates, based on the indication of the relative position, feedback indicating a recommended movement of the transaction object relative to the interface to increase signal strength, and sends the feedback to an output device to output the feedback to indicate the recommended movement. The system reads the information from the transaction object using the interface in response to an increase in signal strength and to the outputting of the feedback.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Block, Inc.
    Inventors: Jason Binder, Matthew Maibach, Cory Douthat, Thomas Byrne
  • Patent number: 11658379
    Abstract: A TE20 launch guidance waveguide hybrid coupler includes a waveguide body, a cavity, a plurality of ports, and a bend along the H-plane. The waveguide body includes a hybrid center portion which is disposed between and is in direct communication with the plurality of ports. The bend along the H-Plane is defined within the hybrid center portion, assists in the launching of the TE20 mode, and results in typically half the axial ratio and mass when compared to traditional hybrid approaches.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 23, 2023
    Assignee: LOCKHEED MARTIN CORPORA TION
    Inventors: Jason Stewart Wrigley, Mark Winebrand
  • Patent number: 11609833
    Abstract: A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Praveen Durga, Parul Bansal
  • Patent number: 11595047
    Abstract: Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 28, 2023
    Assignee: Ciena Corporation
    Inventors: YoungJun Park, Sadok Aouini
  • Patent number: 11429139
    Abstract: A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 30, 2022
    Inventors: Robert Bismuth, Mike Stengle
  • Patent number: 11088680
    Abstract: Methods and apparatus for reducing Miller effect in SiC MOSFETs are provided. An example apparatus includes a plurality of SiC MOSFETs and a Miller current cancellation circuit configured to mitigate Miller current induced by switching transients associated with the plurality of SiC MOSFETS. The Miller current cancellation circuit includes a two-stage voltage sampling circuit configured to sample a drain to source voltage of a SiC MOSFET of the plurality of SiC MOSFETs, a voltage inverting circuit configured to invert the sampled drain to source voltage, and an injection capacitor configured to generate, by way of receiving the inverted sampled drain to source voltage as input, inverse Miller current to mitigate the Miller current within the plurality of SiC MOSFETS.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Shuo Wang, Boyi Zhang
  • Patent number: 10951218
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 16, 2021
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 10212683
    Abstract: A system may be provided and may include a trusted DECT device; and a DECT base station; wherein the trusted DECT device is arranged to send, to the DECT base station, registration allowable DECT device credentials; wherein the DECT base station is arranged to: receive from a requesting DECT device a request for registration of the requesting DECT device to the DECT base station; wherein the request comprises requesting DECT device credentials; register the requesting DECT device to the DECT base station if the requesting DECT device credentials match the registration allowable DECT device credentials; and prevent a registration of the requesting DECT device to the DECT base station if the requesting DECT device credentials differ from the registration allowable DECT device credentials.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 19, 2019
    Assignee: DSP GROUP LTD.
    Inventors: Jochen Kilian, Otmar Rengert
  • Patent number: 10110234
    Abstract: Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 23, 2018
    Assignee: XILINX, INC.
    Inventors: Uma E. Durairajan, Subodh Kumar, Adam Elkins, Ghazaleh Mirjafari, Amitava Majumdar
  • Patent number: 9904346
    Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Ohad Falik, Jose P. Allarey
  • Patent number: 9395412
    Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 19, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9330220
    Abstract: Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Mehrdad E. Dehkordi, Marvin Tom, Sridhar Krishnamurthy, Abhishek Joshi
  • Patent number: 9323642
    Abstract: A calculation method includes calculating, by a processor, a difference between a first value and a second value, the first value being read from a clock counter that counts pulses of a clock signal having a plurality of types of frequencies, supplied to the processor in response to control command to start processing for an unit to be allocated to the processor, the second value being read from the clock counter in response to control command to stop processing.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Miho Kato, Hiroyuki Suzuki, Tsubasa Kitayama, Norio Kurobane
  • Patent number: 9112652
    Abstract: A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: August 18, 2015
    Assignee: IPGOAL MICROELECTRONICS (SICHUAN) CO., LTD.
    Inventors: Ziche Zhang, Zhengxian Zou
  • Publication number: 20150137853
    Abstract: Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Mao-Hsuan Chou
  • Publication number: 20150091617
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 8970254
    Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: March 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Glenn Murphy, Jingcheng Zhuang, Xiaohua Kong, William Knox Ladd
  • Patent number: 8970255
    Abstract: A frequency detection apparatus includes: a constant current generator, arranged for providing a constant current to a voltage output terminal; a first capacitor, coupled between the voltage output terminal and a first reference voltage; a first transistor, which has a first connection terminal coupled to the voltage output terminal, a control terminal coupled to an input signal; a second connection terminal, coupled between the second connection terminal of the first transistor and the first reference voltage; a second transistor, which has a first connection terminal coupled to the second connection terminal of the first transistor, a second connection terminal coupled to the first reference voltage, a control terminal coupled to an inverted input signal, which is obtained by inverting the input signal; wherein a voltage output of the voltage output terminal changes with an input signal frequency of the input signal.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: March 3, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Tsung-Yen Tsai
  • Patent number: 8937496
    Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: January 20, 2015
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Alex S. Warshofsky, Ygal Arbel
  • Patent number: 8913978
    Abstract: A multiphase mixer using a rotary traveling wave oscillator is disclosed. In addition to the oscillator, the mixer includes first and second mixer circuits. The rotary traveling wave oscillator generates a first set of N/2 phase and a second set of N/2 phases, where each phase has a frequency that is a factor of N/2 less than the incoming radio frequency signal. The first set of phases are sine signals and the second set of phases are cosine signals. The first mixer circuit generates a first down-converted signal from the first set of phases and the incoming rf signal. The second mixer circuit generates a second down-converted signal from the second set of phases and the rf signal.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: December 16, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Gregoire Le Grand de Mercey
  • Patent number: 8884663
    Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven J. Kommrusch, Zihno Jusufovic
  • Patent number: 8816781
    Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: August 26, 2014
    Inventor: Phuong Huynh
  • Patent number: 8648622
    Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: February 11, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Michael Baus, Michael Stemmler
  • Patent number: 8643410
    Abstract: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.
    Type: Grant
    Filed: September 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Prashant Bhargava, Mohit Arora, James R. Feddeler, Martin Mienkina
  • Patent number: 8610479
    Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 17, 2013
    Assignee: Parade Technologies, Ltd.
    Inventors: Kochung Lee, Quan Yu, Yuntao Zhu, Lei Xie, Ming Qu
  • Patent number: 8497729
    Abstract: A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 30, 2013
    Assignee: Power Integrations, Inc.
    Inventor: William M. Polivka
  • Patent number: 8384707
    Abstract: An image display system synchronizes the display of images on a plurality of display devices. The method entails generating at a first computer system a first signal representing first image data to be displayed on a first display device, generating at a second computer system a second signal representing second image data to be displayed on a second display device, and a method for synchronizing the first and second image data. The synchronizing method includes using a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: February 26, 2013
    Assignee: RPX Corporation
    Inventors: Joseph P. Kennedy, John A. Klenoski, Greg Sadowski
  • Patent number: 8384440
    Abstract: The high resolution capture (HRCAP) of this invention enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: February 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Alexander Tessarolo, Saya Goud Langadi
  • Patent number: 8368472
    Abstract: A high-accuracy clock signal is generated even when the settings of the clock frequency are changed or there is a variation in power supply, temperature, or the like. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakamura, Kosuke Yayama
  • Patent number: 8354867
    Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: January 15, 2013
    Assignee: National Taiwan University
    Inventors: Shey-Shi Lu, Hsien-Ku Chen
  • Patent number: 8351558
    Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Richard H. Strandberg, Paul Cheng-Po Liang
  • Publication number: 20120306539
    Abstract: A fractional-n clock generator includes a first digital delay line module, a second delay line module, an address generator and a selector. The first delay line module receives a frequency-divided clock signal and generates first delay signals having different phase differences with respect to the clock signal. The second delay line module receives the clock signal and generates second delay signals having different phase differences with respect to the clock signal. The address generator selects one of the first delay signals as an output signal of the first delay line module and one of the second delay signals as an output signal of the second delay line module. The selector selects one of the output signals of the first delay line module and the second delay line module as an output signal. A delay of the first delay line module is different from that of the second delay line module.
    Type: Application
    Filed: May 25, 2012
    Publication date: December 6, 2012
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventor: CHOU MIN CHUNG
  • Patent number: 8326364
    Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: December 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gary F. Chard, T-Pinn R. Koh, Yilun Wang
  • Patent number: 8324941
    Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: December 4, 2012
    Assignee: Power Integrations, Inc.
    Inventor: William M. Polivka
  • Publication number: 20120286825
    Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.
    Type: Application
    Filed: November 26, 2010
    Publication date: November 15, 2012
    Inventors: Michael Baus, Michael Stemmler
  • Patent number: 8302054
    Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: October 30, 2012
    Assignee: Synopsys, Inc.
    Inventors: Mustafa Ispir, Levent Oktem
  • Patent number: 8274313
    Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: September 25, 2012
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 8203363
    Abstract: A frequency detection apparatus and method are provided. The frequency detection apparatus includes a frequency conversion circuit and an analog conversion circuit. The frequency conversion circuit receives an input clock, and generates an analog signal corresponding to a frequency of the input clock based on the frequency of the input clock. The analog conversion circuit is coupled to the frequency conversion circuit, receives the analog signal, and generates a discriminating signal corresponding to the frequency of the input clock based on the analog signal, where the discriminating signal represents a frequency interval of the input clock.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 19, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chen-Chih Huang
  • Patent number: 8169236
    Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 1, 2012
    Assignee: Apple Inc.
    Inventor: Daniel C. Murray
  • Patent number: 8154321
    Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. An evaluation circuit is coupled to the counting circuit. The evaluation circuit is responsive to the count of the cycles of the variable frequency signal after an end of the second time interval.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 10, 2012
    Assignee: Power Integrations, Inc.
    Inventor: William M. Polivka
  • Patent number: 8138801
    Abstract: A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut—1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut—2). The selected frequency source is compared to fpdOut—1 and fpdOut—2 signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Do, Simon Pang
  • Patent number: 8130538
    Abstract: A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: March 6, 2012
    Assignee: Altera Corporation
    Inventors: Peter J. McElheny, Richard G. Smolen, John C. Costello
  • Patent number: 8125249
    Abstract: A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Chul Jeong
  • Patent number: 8125250
    Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: February 28, 2012
    Assignee: Apple Inc.
    Inventor: Daniel C. Murray
  • Patent number: 8040158
    Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: October 18, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshito Suzuki
  • Patent number: 8040156
    Abstract: Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: October 18, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hui Dong Lee, Kwi Dong Kim, Jong Kee Kwon
  • Patent number: 7952344
    Abstract: A frequency characteristic measuring apparatus measures a device under test in which the frequency of an input signal and the frequency of an output signal differ from each other, simplifying the configuration of a tracking generator and peripheral circuits associated with the tracking generator, and simultaneously measuring the characteristics of the input signal and the output signal of the device under test. A spectrum analyzer has mixers, local oscillators and IF sections as first and second measuring units for measuring frequency characteristics of two input signals by performing frequency sweep in correspondence with a first or second frequency range, a mixer and an oscillator as a tracking generator section which operates by being linked to the frequency sweep operation in the first measuring unit, and a section which generates a trigger signal designating measurement start timing.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 31, 2011
    Assignee: Advantest Corporation
    Inventors: Wataru Doi, Yohei Hirakoso
  • Patent number: 7843228
    Abstract: Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 30, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: Joel Brenner
  • Publication number: 20100277204
    Abstract: Methods and apparatus for determining the existence of an external clock over a digital input port on a computer. In one embodiment, the external clock is validated, and a lock is performed when the clock is valid. Whenever a loss of the lock is detected, and, if a re-lock is likely, the apparatus is muted so that audio artifacts that would otherwise be heard are minimized. The methods and apparatus also provide automatic re-locking to the external clock when a sampling rate change is detected.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 4, 2010
    Inventors: Anthony GUETTA, Raymond MONTAGNE, Matthew Xavier MORA
  • Patent number: 7795928
    Abstract: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Christopher Gonzalez, Vinod Ramadurai, Norman Jay Rohrer