Abstract: A high-voltage (HV) compound switch can include coupling circuitry to help provide better slew rate (dV/dt) control, such as to limit electromagnetic energy radiation during switching, which can cause undesirable EMI. Further, efficiency and on-state resistance can be improved by controllably forward-biasing the “normally on” JFET when the compound switch is in an “on” state. In such an on-state, the JFET temperature can be monitored, such as by monitoring the gate-source junction voltage or the gate current of the JFET. Such temperature information can be used for control or other purposes.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A semiconductor switch circuit comprises: a first switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; a second switch pair including two MOSFETs having gates connected one another and sources connected to one another, and a zener diode reversely connected between the gates and sources of the MOSFETs; and a third switch pair comprising two MOSFETs having gates connected to one another and sources connected to one another. The first switch pair and the second switch pair are connected in series between two input/output terminals through a connecting node. The third switch pair is connected to the connecting node between the first switch pair and the second switch pair.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: In a circuit that turns off a fluorescent lamp, clamping circuitry is provided to dissipate energy stored in a ballast when the lamp is being turned off. In a normal state in which the lamp is on, or in a normal state in which the lamp is off, clamping is not performed as long the VDS of a power switch is below a voltage A. In a lamp turn off operation, the switch is turned on for a time period to extinguish the lamp, and is then made to operate as a clamp (operate in its linear region) for a second period of time to dissipate energy that was stored in the ballast. Clamping in the linear region continues for VDS voltages down to B as ballast energy is dissipated, where B is smaller than A. By clamping down to the lower voltage B, re-ignition of the lamp is prevented.

Abstract: A circuit and method for driving a field effect transistor is disclosed. A switching circuit includes a driver device having a signal input, a supply voltage input, and an output. The driver output is coupled to a JFET. A converter couples to the JFET and provides an output of the switching circuit. When enabled, a switching device couples this switching circuit output to the gate of the JFET, thus causing the JFET to be driven into conduction.

Abstract: A composite field effect transistor, in accordance with one embodiment, includes a zener diode, a junction field effect transistor and a metal-oxide-semiconductor field effect transistor. A gate of the junction field effect transistor is coupled to an anode of the zener diode. A cathode of the zener diode is coupled to a gate of the metal-oxide-semiconductor field effect transistor. A drain of the metal-oxide-semiconductor field effect transistor is coupled to a source of the junction field effect transistor.

Abstract: A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor of a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract: In one aspect of the present invention a gate drive circuit is disclosed. The gate drive circuit includes a high voltage and low voltage energy source, a power transistor, a switching transistor, and a charging capacitor. The charging capacitor stores energy from the low voltage energy source. The gate drive circuit further includes a circuit that biases the switching transistor OFF which causes the low voltage energy stored in the capacitor to bias the power transistor ON to transfer high voltage energy to the load. The circuit additionally biases the switching transistor ON which biases the power transistor OFF to block the transfer of high voltage energy. Finally, a protection device is included to limit the power transistor voltage to a maximum voltage level in response to the power transistor being biased ON.

Abstract: A plurality of Zener diodes are connected between two electrodes of a transistor as the protector of the transistor to obtain a predetermined breakdown voltage. Each Zener diode has a breakdown of 5 V whose temperature coefficient is substantially zero.

Abstract: A snubbing clamp network (14) is disclosed which comprises a gate voltage clamp (16) having an input and an output, the output connected to a first node, a gate-source voltage clamp (18) having an input connected to the first node and an output connected to the second node, and voltage reference (20) having an output connected to the input of the gate voltage clamp (16).

Abstract: An isolated MOSFET gate drive includes circuitry to provide a negative gate bias during the off time of the MOSFET to enhance its immunity to inadvertent turn-on. The bias is generated by a self contained two terminal passive network which may be "floated" at any potential with respect to ground. This bias is automatically generated through the action of the network to the gate drive waveform, eliminating the need for an external bias supply to provide this voltage. The bias supply is located locally, thus eliminating the need for long interconnects which may interfere with circuit operation. The bias network in one implementation is a combination of a capacitor and non-linear semiconductor device with a fixed voltage breakdown characteristic. This two-component implementation maintains the capability of producing systems with high packaging densities.