Abstract: A method for actively discharging an electrical energy storage device by means of an electrical circuit arrangement which comprises at least one half bridge comprising two switching elements, wherein the half bridge is connected in parallel with the energy storage device and wherein the switching elements each have a switchable section, the electrical resistance of which can be set in a transmission mode of the switching element by means of a control voltage of the switching element, wherein, in order to discharge the energy storage device, the level of the control voltages of the switchable sections of the switching elements in transmission mode and/or the ratio between a switched-on duration in which the switchable sections of the switching elements are operated in transmission mode during the discharge, and a switched-off duration in which the switchable sections of the switching elements are operated in a blocking mode during the discharge can be set as a function of a discharge current specification desc

Abstract: Embodiments of the disclosure provide a control amplification circuit, a sensitive amplifier and a semiconductor memory. The control amplification circuit includes: a power consumption control circuit, configured to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; an isolating circuit, configured to determine a control instruction signal and generate an isolation control signal according to the control instruction signal; and an amplification circuit, configured to receive the first reference signal, the isolation control signal and a signal to be processed, and process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal.

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.

Abstract: A switch including a transistor to be protected, and a Miller effect protection unit including a protection transistor, the drain of the protection transistor being connected to the gate of the transistor to be protected, the source of the protection transistor being connected to the source of the transistor to be protected, a linking circuit, the linking circuit being a high-pass filter arranged between the gate of the protection transistor and the drain of the transistor to be protected, and a control circuit interposed between the gate of the protection transistor and the source of the transistor to be protected.

Abstract: A control amplifying circuit includes a power supply output circuit, an isolation control circuit and an amplifying circuit. The power supply output circuit is configured to receive a power supply switching signal, and select one preset voltage value from at least two preset voltage values according to the power supply switching signal to output as a preset power supply signal. The isolation control circuit is configured to receive a control command signal and the preset power supply signal, and generate an isolation control signal according to the control command signal. The amplifying circuit is configured to receive the isolation control signal and a signal to be processed, and amplify the signal to be processed based on the isolation control signal to obtain a target amplified signal.

Abstract: A magnetic tape cartridge includes a case that accommodates a magnetic tape on which a plurality of servo bands and a plurality of data bands are formed, servo patterns being recorded in the servo bands, and a memory provided in the case. The memory stores servo pattern interval-related information related to a servo pattern interval determined for each of the plurality of data bands included in the magnetic tape. The servo pattern interval is commonly used for a plurality of division areas obtained by dividing the data band in a width direction of the magnetic tape, and is a representative interval between a first servo pattern and a second servo pattern.

Abstract: The invention relates to a signal isolation and conversion circuit and a control apparatus. The signal isolation and conversion circuit comprises a pulse signal generating circuit and an optical coupling complementary isolation circuit connected with the pulse signal generating circuit; the pulse signal generating circuit is used for receiving an input signal and converting the input signal into a pulse signal; the optical coupling complementary isolation circuit comprises at least two photocouplers, and the at least two photocouplers are switched on or off according to the pulse signal so as to transmit the pulse signal to the output end of the signal isolation and conversion circuit. By arranging the optical coupling complementary isolation circuit, the problems of transmission delay, transmission signal distortion and light attenuation and temperature drift of the light-emitting diode in the optocoupler are effectively solved, the timeliness of isolation signal transmission is improved.

Abstract: An electronic device is provided including a connector comprising a plurality of terminals, the connector being configured to be connected with an external device; a circuit electrically connected to at least a subset of the plurality of terminals; and a processor electrically connected to the circuit, wherein the processor is configured to detect a connection of the external device through the connector, detect a first impedance of a first electrical path including a first terminal of the plurality of terminals, detect a second impedance of a second electrical path including a second terminal of the plurality of terminals, and determine a connection direction of the external device connected through the connector, based on the first impedance and the second impedance.

Abstract: An electronic circuit includes an output, and a first supply circuit and a second supply circuit, which are each connected to the output. The first supply circuit and the second supply circuit each include a supply input; a first circuit node; a first electronic switch; a first rectifier element connected in parallel with the first electronic switch; at least one second electronic switch that is connected between the supply input and the first circuit node; at least one second rectifier element that is connected in parallel with the at least one second switch, wherein the at least one second rectifier element and the first rectifier element are connected in antiseries with one another; and a control circuit. The control circuit activates the first switch and the second switch and receives a supply voltage from the first circuit node at a supply input.

Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.

Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: A semiconductor device is provided. The semiconductor device includes an integrated circuit that senses a voltage of a battery cell and outputs a control signal; a charge switch that is electrically coupled to the integrated circuit and interrupts a charge path according to the control signal output from the integrated circuit; at least one first lead electrically coupled to the integrated circuit; a second lead electrically coupled to the charge switch; and a sealing portion that seals the integrated circuit, charge switch, the at least one first lead and the second lead.

Abstract: A composite semiconductor switching device includes: a first semiconductor element that incurs switching losses when performing switching operation of turning on and off; a second semiconductor element that is parallelly connected to the first semiconductor element and incurs switching losses larger than the first semiconductor element when performing switching operations of turning on and off; and a controller that operates in order of giving a first on-command signal to the first semiconductor element, giving a second on-command signal to the second semiconductor element, deactivating the first on-command signal, giving a third on-command signal to the first semiconductor element, and deactivating the second on-command signal.

Abstract: A highly linear, variable capacitor array constructed from multiple cells. Each cell includes a pair of passive, capacitor components connected in anti-parallel. The capacitor components may be Metal Oxide Semiconductor (MOS) capacitors. A control circuit applies bias voltages to bias voltage terminals associated with each capacitor component, to thereby control the overall capacitance of the array.

Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.

Abstract: An RF pulse signal generation switching circuit for controlling an output of a power FET for amplifying a high frequency signal to generate an RF pulse signal that is the high frequency signal pulse formed into a pulse-wave shape is provided. The circuit includes first and third n-type FETs of which gates are inputted with a control pulse that supplies a rise timing and a fall timing of a pulse, and a second n-type FET of which a gate is connected with a drain of the first FET. A source of the first FET and a source of the third FET are grounded, respectively. The drain of the first FET is applied with a first drive voltage via a resistor. A drain of the second FET is applied with a second drive voltage. A source of the second FET is connected with a drain of the third FET and the connection point therebetween is connected with the power FET. A capacitor is connected between the connection point and an end of the resistor from which the first drive voltage is applied.

Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

Abstract: A circuit performs a method for controlling turn-off of a semiconductor switching element. The method includes determining at least one operating parameter for the semiconductor switching element during an operating cycle and determining a gate discharge current based on the at least one operating parameter. The method further includes supplying the gate discharge current to a gate of the semiconductor switching element during a subsequent operating cycle to turn off the semiconductor switching element.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: Devices and methods for electrically decoupling a solar module from a solar system are described. In one embodiment, a solar system includes a string of a plurality of solar modules coupled with an inverter through a DC power line. An AC input is coupled with the DC power line. A device is also included and is configured to provide a closed circuit for one of the plurality of solar modules if an AC signal voltage from the AC input is present on the DC power line, and is configured to provide an open circuit for the one of the plurality of solar modules if no AC signal voltage from the AC input is present on the DC power line.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: An embodiment of an apparatus, such as a circuit breaker, includes an input node, an output node, and a digital circuit. The input node is configured to receive an input voltage, and the output node is coupled to the input node and is configured to carry an output current. And the digital circuit is configured to uncouple the output node from the input node in response to a power drawn from the input node exceeding a threshold.

Abstract: A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.

Abstract: The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.

Abstract: A device includes a controller configured to regulate one or more voltages applied to a gate of an insulated gate bipolar transistor (IGBT). The controller is configured to receive one or more voltage values associated with the IGBT, and generate a gating signal and transmit the gating signal to the IGBT. The gating signal is configured to activate or deactivate the IGBT. The controller is configured to generate a voltage clamping signal and transmit the voltage clamping signal to activate or deactivate an active switching device. The active switching device is configured to periodically limit the one or more voltage values associated with the IGBT based at least in part on one or more characteristics of the voltage clamping signal.

Abstract: A system for scalable voltage ramp control for power supply systems. A system may comprise at least power supply circuitry, digital-to-analog (D/A) converter circuitry and a controller. The power supply circuitry may be configured to output a voltage to a load based on an input voltage provided by the D/A converter. The controller may be configured to control the D/A converter (e.g., to cause the D/A converter to provide the input voltage to the power supply circuitry) using a large range voltage ramp-up or a small range voltage ramp-up. Utilization of the large range voltage ramp-up or the small range voltage ramp-up by the controller may be based on, for example, a threshold voltage.

Abstract: In a driver, a changing module changes a rate of discharging the control terminal of a switch at least between a first value and a second value lower than the first value. A measuring module measures a value of a parameter as a function of a current flowing through the conductive path of the switch during a drive signal being in an on state. A control module controls the changing module, as a function of the value of the parameter, to select the first value or the second value as the rate of discharging the control terminal of the switch upon the drive signal directing a change from the on state of the switch to an off state thereof. The control module discharges the control terminal of the switch using the selected value as the rate of discharging the control terminal of the switch.

Abstract: In a driver, a charging module stores negative charge on the gate of a switching element via a normal electrical path to charge the switching element upon a drive signal representing change of an on state to an off state. This shifts the on state of the switching element to the off state. An adjusting module changes a value of a parameter correlating with a charging rate of the switching element through the normal electrical path as a function of an input signal to the driver. The input signal represents a current flowing through the conductive path, a voltage across both ends of the conductive path, or a voltage at the gate. A disabling module disables the adjusting module from changing the value of the parameter if the drive signal represents the on state of the switching element.

Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.

Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.

Abstract: The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has field application electrode that is connected to semiconductor substrate with insulating film interposed therebetween. Field control unit of driving unit is connected to field application electrode and source electrode of switching element, and applies a bias voltage Ve between field application electrode and source electrode. Field control unit applies an electric field from field application electrode to a hetero-junction interface of semiconductor substrate, by applying the bias voltage Ve exceeding a threshold value to switching element. In short, in the ON state of switching element, the electric field that is applied from field application electrode to semiconductor substrate works to increase electron concentration in a channel region by a field effect and decrease the ON resistance of switching element.

Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.

Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.

Abstract: A hybrid switching circuit includes first and second switching devices containing first and second unequal bandgap semiconductor materials. These switching devices, which support parallel conduction in response to first and second control signals, are three or more terminal switching devices of different type. For example, the first switching device may be a three or more terminal wide bandgap switching device selected from a group consisting of JFETs, IGFETs and high electron mobility transistors HEMTs, and the second switching device may be a Si-IGBT. A control circuit is also provided, which is configured to drive the first and second switching devices with first and second periodic control signals having first and second unequal duty cycles. The first duty cycle may be greater than the second duty cycle and the active phases of the second periodic control signal may occur exclusively within the active phases of the first periodic control signal.

Abstract: A device includes a controller configured to regulate one or more voltages applied to a gate of an insulated gate bipolar transistor (IGBT). The controller is configured to receive one or more voltage values associated with the IGBT, and generate a gating signal and transmit the gating signal to the IGBT. The gating signal is configured to activate or deactivate the IGBT. The controller is configured to generate a voltage clamping signal and transmit the voltage clamping signal to activate or deactivate an active switching device. The active switching device is configured to periodically limit the one or more voltage values associated with the IGBT based at least in part on one or more characteristics of the voltage clamping signal.

Abstract: The present invention provides an array substrate, a driving method and a display device. The array substrate comprises a plurality of gate lines. A first gate line of the two adjacent gate lines is coupled to a first switch unit and a second gate line is coupled to a second switch unit. The first switch unit and the second switch unit are coupled to a control line, and are coupled to a gate drive output channel. The second switch unit is turned off when the first switch unit is turned on under control of the control line, and the first switch unit is turned off when the second switch is turned on under control of the control line. According to the present invention, it is able to effectively reduce the number of the gate drive ICs and thereby to reduce the cost.

Abstract: A multiplexer and a dynamic bias switch thereof are provided. The dynamic bias switch includes a switch transistor and a dynamic bulk bias (DBB) unit. A first terminal and a second terminal of the switch transistor are respectively coupled to a first terminal and a second terminal of the dynamic bias switch. A bulk of the switch transistor is coupled to the DBB unit. The DBB unit selectively couples the first terminal or the second terminal of the switch transistor to the bulk of the switch transistor.

Abstract: A disconnecting apparatus for direct current interruption between a direct current source and an electrical device, in particular between a photovoltaic generator and an inverter, has a current-conducting mechanical switching contact and semiconductor electronics connected in parallel with the switching contact. The semiconductor electronics are non-conducting when the switching contact is closed, wherein a control input of the semiconductor electronics is wired with the switching contact in such a way that, when the switching contact opens, an arc voltage generated as a result of an arc via the switching contact switches the semiconductor electronics to become conducting.

Abstract: There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices and at least one first diode device individually connected to control terminals of the plurality of first switching devices to enable or block signal flow between a common port transmitting and receiving a first high frequency signal and a first port inputting and outputting the first high frequency signal; and a second signal transferring unit including a plurality of second switching devices and at least one second diode device individually connected to control terminals of the plurality of second switching devices to enable or block signal flow between the common port transmitting and receiving a second high frequency signal and a second port inputting and outputting the second high frequency signal.

Abstract: Power gating circuits. A transistor stack is coupled between a voltage supply to provide a gated supply voltage. The supply voltage is greater than the maximum junction voltage of the individual transistors in the transistor stack. Termination circuitry for input/output (I/O) lines coupled to operate using the gated supply voltage. The termination circuitry comprising at least a resistive element coupled between an I/O interface and a termination voltage supply.

Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.

Abstract: An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element mounting unit, a first conductor, a semiconductor element, a first connection and a second connection. The first conductor is provided around the semiconductor element mounting unit. The semiconductor element is provided on the semiconductor element mounting unit and includes a first switch element and a second switch element provided parallel to the first switch element. The first connection and the second connection are provided on the first switch element side of an imaginary boundary line obtained by extending a boundary between the first switch element and the second switch element. The first connection and the second connection are electrically connected to the first switch element and the second switch element, respectively, and electrically connected to the first conductor.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.