Utilizing Three Or More Electrode Solid-state Device Patents (Class 327/419)
  • Patent number: 9602060
    Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: March 21, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Oleksandr Gorbachov, Huan Zhao, Lisette L. Zhang, Lothar Musiol, Yongxi Qian
  • Patent number: 9548732
    Abstract: A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Thierry Sicard, Philippe Perruchoud
  • Patent number: 9224721
    Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 29, 2015
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Patent number: 9028987
    Abstract: A semiconductor device is provided. The semiconductor device includes an integrated circuit that senses a voltage of a battery cell and outputs a control signal; a charge switch that is electrically coupled to the integrated circuit and interrupts a charge path according to the control signal output from the integrated circuit; at least one first lead electrically coupled to the integrated circuit; a second lead electrically coupled to the charge switch; and a sealing portion that seals the integrated circuit, charge switch, the at least one first lead and the second lead.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 12, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Bongyoung Kim
  • Publication number: 20150116024
    Abstract: A composite semiconductor switching device includes: a first semiconductor element that incurs switching losses when performing switching operation of turning on and off; a second semiconductor element that is parallelly connected to the first semiconductor element and incurs switching losses larger than the first semiconductor element when performing switching operations of turning on and off; and a controller that operates in order of giving a first on-command signal to the first semiconductor element, giving a second on-command signal to the second semiconductor element, deactivating the first on-command signal, giving a third on-command signal to the first semiconductor element, and deactivating the second on-command signal.
    Type: Application
    Filed: April 6, 2012
    Publication date: April 30, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventor: Junichiro Ishikawa
  • Patent number: 9019007
    Abstract: A highly linear, variable capacitor array constructed from multiple cells. Each cell includes a pair of passive, capacitor components connected in anti-parallel. The capacitor components may be Metal Oxide Semiconductor (MOS) capacitors. A control circuit applies bias voltages to bias voltage terminals associated with each capacitor component, to thereby control the overall capacitance of the array.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 28, 2015
    Assignee: Newlans, Inc.
    Inventors: Dev V. Gupta, Zhiguo Lai
  • Patent number: 9000829
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 8994579
    Abstract: An RF pulse signal generation switching circuit for controlling an output of a power FET for amplifying a high frequency signal to generate an RF pulse signal that is the high frequency signal pulse formed into a pulse-wave shape is provided. The circuit includes first and third n-type FETs of which gates are inputted with a control pulse that supplies a rise timing and a fall timing of a pulse, and a second n-type FET of which a gate is connected with a drain of the first FET. A source of the first FET and a source of the third FET are grounded, respectively. The drain of the first FET is applied with a first drive voltage via a resistor. A drain of the second FET is applied with a second drive voltage. A source of the second FET is connected with a drain of the third FET and the connection point therebetween is connected with the power FET. A capacitor is connected between the connection point and an end of the resistor from which the first drive voltage is applied.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: March 31, 2015
    Assignee: FURUNO Electric Company Ltd.
    Inventor: Tomonao Kobayashi
  • Patent number: 8988133
    Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20150061751
    Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 5, 2015
    Inventors: Boris RESHETNYAK, Dante E. PICCONE, Victor TEMPLE
  • Publication number: 20150061750
    Abstract: A circuit performs a method for controlling turn-off of a semiconductor switching element. The method includes determining at least one operating parameter for the semiconductor switching element during an operating cycle and determining a gate discharge current based on the at least one operating parameter. The method further includes supplying the gate discharge current to a gate of the semiconductor switching element during a subsequent operating cycle to turn off the semiconductor switching element.
    Type: Application
    Filed: August 31, 2013
    Publication date: March 5, 2015
    Inventors: IBRAHIM S. KANDAH, FRED T. BRAUCHLER, STEVEN R. EVERSON
  • Patent number: 8963375
    Abstract: Devices and methods for electrically decoupling a solar module from a solar system are described. In one embodiment, a solar system includes a string of a plurality of solar modules coupled with an inverter through a DC power line. An AC input is coupled with the DC power line. A device is also included and is configured to provide a closed circuit for one of the plurality of solar modules if an AC signal voltage from the AC input is present on the DC power line, and is configured to provide an open circuit for the one of the plurality of solar modules if no AC signal voltage from the AC input is present on the DC power line.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 24, 2015
    Assignee: SunPower Corporation
    Inventor: David DeGraaff
  • Patent number: 8952750
    Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Publication number: 20150028935
    Abstract: An embodiment of an apparatus, such as a circuit breaker, includes an input node, an output node, and a digital circuit. The input node is configured to receive an input voltage, and the output node is coupled to the input node and is configured to carry an output current. And the digital circuit is configured to uncouple the output node from the input node in response to a power drawn from the input node exceeding a threshold.
    Type: Application
    Filed: July 24, 2014
    Publication date: January 29, 2015
    Inventors: Salvatore PANTANO, Marco MARTINI
  • Patent number: 8933746
    Abstract: A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 13, 2015
    Assignee: Astronics Advanced Electronic Systems Corp.
    Inventors: Frederick J. Potter, Raymond Moravec
  • Patent number: 8928363
    Abstract: The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Ayumu Hatanaka, Kaoru Kato, Katsumi Ishikawa, Naoki Maru
  • Patent number: 8907716
    Abstract: A device includes a controller configured to regulate one or more voltages applied to a gate of an insulated gate bipolar transistor (IGBT). The controller is configured to receive one or more voltage values associated with the IGBT, and generate a gating signal and transmit the gating signal to the IGBT. The gating signal is configured to activate or deactivate the IGBT. The controller is configured to generate a voltage clamping signal and transmit the voltage clamping signal to activate or deactivate an active switching device. The active switching device is configured to periodically limit the one or more voltage values associated with the IGBT based at least in part on one or more characteristics of the voltage clamping signal.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 9, 2014
    Assignee: General Electric Company
    Inventors: Jun Zhu, Robert Gregory Wagoner, Huibin Zhu, Chengjun Wang
  • Patent number: 8860595
    Abstract: A system for scalable voltage ramp control for power supply systems. A system may comprise at least power supply circuitry, digital-to-analog (D/A) converter circuitry and a controller. The power supply circuitry may be configured to output a voltage to a load based on an input voltage provided by the D/A converter. The controller may be configured to control the D/A converter (e.g., to cause the D/A converter to provide the input voltage to the power supply circuitry) using a large range voltage ramp-up or a small range voltage ramp-up. Utilization of the large range voltage ramp-up or the small range voltage ramp-up by the controller may be based on, for example, a threshold voltage.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 14, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Siqiang Fan, Andrew Kameya, Bin Zhao
  • Patent number: 8841870
    Abstract: In a driver, a changing module changes a rate of discharging the control terminal of a switch at least between a first value and a second value lower than the first value. A measuring module measures a value of a parameter as a function of a current flowing through the conductive path of the switch during a drive signal being in an on state. A control module controls the changing module, as a function of the value of the parameter, to select the first value or the second value as the rate of discharging the control terminal of the switch upon the drive signal directing a change from the on state of the switch to an off state thereof. The control module discharges the control terminal of the switch using the selected value as the rate of discharging the control terminal of the switch.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: September 23, 2014
    Assignee: Denso Corporation
    Inventors: Junichi Fukuta, Tsuneo Maebara
  • Patent number: 8829976
    Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasushi Kuwabara, Katsuhiko Saito, Masahiro Fukuda
  • Patent number: 8829836
    Abstract: In a driver, a charging module stores negative charge on the gate of a switching element via a normal electrical path to charge the switching element upon a drive signal representing change of an on state to an off state. This shifts the on state of the switching element to the off state. An adjusting module changes a value of a parameter correlating with a charging rate of the switching element through the normal electrical path as a function of an input signal to the driver. The input signal represents a current flowing through the conductive path, a voltage across both ends of the conductive path, or a voltage at the gate. A disabling module disables the adjusting module from changing the value of the parameter if the drive signal represents the on state of the switching element.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: September 9, 2014
    Assignee: Denso Corporation
    Inventors: Junichi Fukuta, Tsuneo Maebara, Yoshiyuki Hamanaka
  • Patent number: 8816264
    Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 26, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Guangbin Zhang, Dennis Lee
  • Patent number: 8797086
    Abstract: The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has field application electrode that is connected to semiconductor substrate with insulating film interposed therebetween. Field control unit of driving unit is connected to field application electrode and source electrode of switching element, and applies a bias voltage Ve between field application electrode and source electrode. Field control unit applies an electric field from field application electrode to a hetero-junction interface of semiconductor substrate, by applying the bias voltage Ve exceeding a threshold value to switching element. In short, in the ON state of switching element, the electric field that is applied from field application electrode to semiconductor substrate works to increase electron concentration in a channel region by a field effect and decrease the ON resistance of switching element.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Panasonic Corporation
    Inventors: Yosiaki Honda, Yuichi Inaba
  • Patent number: 8779839
    Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 15, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Patent number: 8779837
    Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Gotou, Masanori Hayashi, Takashi Kishida, Kouji Yamato
  • Publication number: 20140184308
    Abstract: A device includes a controller configured to regulate one or more voltages applied to a gate of an insulated gate bipolar transistor (IGBT). The controller is configured to receive one or more voltage values associated with the IGBT, and generate a gating signal and transmit the gating signal to the IGBT. The gating signal is configured to activate or deactivate the IGBT. The controller is configured to generate a voltage clamping signal and transmit the voltage clamping signal to activate or deactivate an active switching device. The active switching device is configured to periodically limit the one or more voltage values associated with the IGBT based at least in part on one or more characteristics of the voltage clamping signal.
    Type: Application
    Filed: February 14, 2013
    Publication date: July 3, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jun Zhu, Robert Gregory Wagoner, Huibin Zhu, Chengjun Wang
  • Publication number: 20140185346
    Abstract: A hybrid switching circuit includes first and second switching devices containing first and second unequal bandgap semiconductor materials. These switching devices, which support parallel conduction in response to first and second control signals, are three or more terminal switching devices of different type. For example, the first switching device may be a three or more terminal wide bandgap switching device selected from a group consisting of JFETs, IGFETs and high electron mobility transistors HEMTs, and the second switching device may be a Si-IGBT. A control circuit is also provided, which is configured to drive the first and second switching devices with first and second periodic control signals having first and second unequal duty cycles. The first duty cycle may be greater than the second duty cycle and the active phases of the second periodic control signal may occur exclusively within the active phases of the first periodic control signal.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Eaton Corporation
    Inventors: Yu Liu, Andraw Ho, Nash Lee, Slobodan Krstic
  • Publication number: 20140159798
    Abstract: The present invention provides an array substrate, a driving method and a display device. The array substrate comprises a plurality of gate lines. A first gate line of the two adjacent gate lines is coupled to a first switch unit and a second gate line is coupled to a second switch unit. The first switch unit and the second switch unit are coupled to a control line, and are coupled to a gate drive output channel. The second switch unit is turned off when the first switch unit is turned on under control of the control line, and the first switch unit is turned off when the second switch is turned on under control of the control line. According to the present invention, it is able to effectively reduce the number of the gate drive ICs and thereby to reduce the cost.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 12, 2014
    Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xin Duan
  • Publication number: 20140152375
    Abstract: A multiplexer and a dynamic bias switch thereof are provided. The dynamic bias switch includes a switch transistor and a dynamic bulk bias (DBB) unit. A first terminal and a second terminal of the switch transistor are respectively coupled to a first terminal and a second terminal of the dynamic bias switch. A bulk of the switch transistor is coupled to the DBB unit. The DBB unit selectively couples the first terminal or the second terminal of the switch transistor to the bulk of the switch transistor.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Wei-Kai Tseng
  • Patent number: 8742828
    Abstract: A disconnecting apparatus for direct current interruption between a direct current source and an electrical device, in particular between a photovoltaic generator and an inverter, has a current-conducting mechanical switching contact and semiconductor electronics connected in parallel with the switching contact. The semiconductor electronics are non-conducting when the switching contact is closed, wherein a control input of the semiconductor electronics is wired with the switching contact in such a way that, when the switching contact opens, an arc voltage generated as a result of an arc via the switching contact switches the semiconductor electronics to become conducting.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 3, 2014
    Assignee: Ellenberger & Poensgen GmbH
    Inventors: Michael Naumann, Thomas Zitzelsperger, Frank Gerdinand
  • Publication number: 20140145782
    Abstract: There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices and at least one first diode device individually connected to control terminals of the plurality of first switching devices to enable or block signal flow between a common port transmitting and receiving a first high frequency signal and a first port inputting and outputting the first high frequency signal; and a second signal transferring unit including a plurality of second switching devices and at least one second diode device individually connected to control terminals of the plurality of second switching devices to enable or block signal flow between the common port transmitting and receiving a second high frequency signal and a second port inputting and outputting the second high frequency signal.
    Type: Application
    Filed: February 13, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Chan Yong JEONG
  • Publication number: 20140126090
    Abstract: Power gating circuits. A transistor stack is coupled between a voltage supply to provide a gated supply voltage. The supply voltage is greater than the maximum junction voltage of the individual transistors in the transistor stack. Termination circuitry for input/output (I/O) lines coupled to operate using the gated supply voltage. The termination circuitry comprising at least a resistive element coupled between an I/O interface and a termination voltage supply.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Inventors: Christopher P. Mozak, Hong Yun Tan
  • Patent number: 8710900
    Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 29, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Publication number: 20140098297
    Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Julie Lynn Stultz, Steven Macaluso, Enrique O. Rodriguez
  • Publication number: 20140097884
    Abstract: An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.
    Type: Application
    Filed: June 15, 2011
    Publication date: April 10, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Valery Neiman, Michael Priel
  • Patent number: 8681275
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element mounting unit, a first conductor, a semiconductor element, a first connection and a second connection. The first conductor is provided around the semiconductor element mounting unit. The semiconductor element is provided on the semiconductor element mounting unit and includes a first switch element and a second switch element provided parallel to the first switch element. The first connection and the second connection are provided on the first switch element side of an imaginary boundary line obtained by extending a boundary between the first switch element and the second switch element. The first connection and the second connection are electrically connected to the first switch element and the second switch element, respectively, and electrically connected to the first conductor.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kamishinbara, Yuichi Goto
  • Publication number: 20140070871
    Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Inventor: Wayne Shumaker
  • Publication number: 20140049284
    Abstract: A test device for testing a semiconductor device including a TSV may comprise a ring oscillator including a plurality of inverters, a switch selectively connecting an output node of an inverter of the plurality of inverters and the TSV, and a controller controlling the switch.
    Type: Application
    Filed: July 18, 2013
    Publication date: February 20, 2014
    Applicants: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
    Inventors: Jun-So Pak, Jun-Ho Lee, Joung-Ho Kim
  • Patent number: 8648643
    Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: February 11, 2014
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Publication number: 20140035656
    Abstract: According to one embodiment, a semiconductor device includes: a first switching element; a first interconnection; a first resistor; and a second interconnection. The first switching element includes a first control terminal, a first electrode terminal, and a first conductor terminal. The second switching element includes a second control terminal, a second electrode terminal, and a second conductor terminal. The first interconnection includes a first through a fourth interterminal interconnections. The first resistor is connected at a first end to the first control terminal. The second resistor is connected at a first end to the second control terminal and is connected at a second end to a second end of the first resistor. The second interconnection is provided between the first electrode terminal and the second electrode terminal and/or between the first control terminal and the second control terminal.
    Type: Application
    Filed: March 7, 2013
    Publication date: February 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazuto Takao
  • Publication number: 20140034808
    Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Guangbin Zhang, Dennis Lee
  • Publication number: 20140015592
    Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventor: Rolf Weis
  • Publication number: 20140015593
    Abstract: An RF switch includes a switchable RF transistor. The switchable RF transistor includes a stripe of a plurality of adjacent RF transistor fingers and at least one non-switchable dummy transistor that is arranged at an end of the stripe of the switchable RF transistor.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Franz Weiss, Hans Taddiken, Nikolay Ilkov, Winfried Bakalski, Jochen Essel, Herbert Kebinger
  • Publication number: 20130343138
    Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.
    Type: Application
    Filed: August 28, 2013
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Dariusz KOWALCZYK
  • Patent number: 8610489
    Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Tyler Daigle, Julie Lynn Stultz, Kenneth P. Snowdon
  • Publication number: 20130314138
    Abstract: An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anis M. Jarrar, Hector Sanchez
  • Publication number: 20130314147
    Abstract: A semiconductor processing device (10) of the present invention includes a processing circuit (1), a digital-analog conversion circuit (2), an output control circuit (3), at least one output port circuit (4), a connection control circuit (5), and an output switch circuit (6). The output port circuit (4) includes an output buffer (41), a first switch element (SW1), and a second switch element (SW2, SW3). When the second switch element is connected to the side of an output amplifier (42), the output port circuit (4) controls the ON resistance of a P channel MOS transistor (41a) and an N channel MOS transistor (41b) based on a signal amplified at the output amplifier (42) to output an analog signal from the output buffer (41).
    Type: Application
    Filed: March 28, 2012
    Publication date: November 28, 2013
    Inventors: Nobuo Shimizu, Yutaka Takikawa
  • Patent number: 8589101
    Abstract: An apparatus for measuring RMS values of burst-fired currents includes a current sensor having a signal output, an analog-to-digital (A/D) converter coupled to the signal output of the current sensor, a digital processor coupled to an output of the A/D converter, and a digital memory coupled to the digital processor. Code segments stored in the digital memory are executable on the digital processor and implement a process of: a) initially sampling the output of the A/D converter; b) determining from the initial sampling a burst-fired current pattern; c) sampling the output of the A/D converter N times within a burst-fired current pattern to provide N samples; and d) calculating an RMS value from the N samples.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 19, 2013
    Assignee: Neilsen-Kuljian, Inc.
    Inventors: Huy D. Nguyen, Tom Lik-Chung Lee
  • Publication number: 20130300485
    Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Darmin Jin, William Chau, Brian Cheung
  • Publication number: 20130293281
    Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Applicant: Intel Mobile Communications GmbH
    Inventors: Thomas Baumann, Christian Pacha, Peter Mahrla