Abstract: I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

Abstract: A polycrystalline diamond abrasive element, particularly a cutting element, comprises a table of polycrystalline diamond bonded to a substrate, particularly a cemented carbide substrate, along a non-planar interface. The polycrystalline diamond abrasive element is characterized by the nonplanar interface having a cruciform configuration, the polycrystalline diamond having a high wear-resistance, and the polycrystalline diamond having a region adjacent the working surface lean in catalysing material and a region rich in catalysing material. The polycrystalline diamond cutters have improved wear resistance, impact strength and cutter life than prior art cutters.

Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.

Abstract: An N-level rectifier, wherein N is a number of voltage levels of the rectifier, includes an input; a plurality of switching devices connected in parallel, wherein the plurality of switching devices are connected to the input, wherein a number of the plurality of switching devices is equal to N?2; and a plurality of capacitors connected in series, wherein the plurality of capacitors are connected to the plurality of switching devices, wherein a number of the plurality of capacitors is equal to N?1, and wherein the plurality of capacitors are connected to an output of the N-level rectifier; wherein N is greater than three.

Abstract: A half-bridge circuit in accordance with an embodiment of the present application includes an input voltage terminal operable to receive an input voltage, a first bi-directional switch, a second bi-directional switch connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected to the input voltage terminal such that the input voltage is provided across the first and second bi-directional switches and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at an midpoint node positioned between the first bi-directional switch and the second bi-directional switch. The first bi-directional switch and the second bi-directional switch are high electron mobility transistors structured to allow for conduction in two directions when ON and to prevent conduction in any direction when OFF.

Abstract: A threshold element enabling a logical operation with fewer transistors and easy design and setting of an element weight and a threshold value is provided. In a threshold element of the present invention, MIS (Metal Insulator Semiconductor) transistors each passing a drain current upon excitation corresponding to weight &ohgr;i of input Xi obtained from a logical expression Y=Sign(&Sgr;&ohgr;iXi−1) derived from Y=F(Xi) thereof are connected in parallel. A terminal for transmitting an input signal Xi corresponding to each of the transistors is connected to the gate electrode thereof. By this input signal, excitation of each of the transistors is controlled. An output voltage based on a sum of the drain currents from the transistors is compared with a threshold value by a comparing inverter, and a comparison result is output.