Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

Abstract: In various embodiments, a device is provided. The device includes a substrate having a first side and a second side opposite the first side. The substrate includes a plurality of driver circuits at the first side of the substrate. Each of the plurality of driver circuits is configured to drive a current from the first side of the substrate to the second side of the substrate. The device further includes at least one load interface at the second side of the substrate. The at least one load interface is configured to couple the current from the plurality of the driver circuits to a plurality of loads at the second side of the substrate.

Abstract: A switch includes a first switching member and a latch circuit. A first terminal of the first switching member is electrically connected to a power source, while a second terminal thereof is electrically connected to a loading. The latch circuit includes a first transistor and a second transistor which are mutually electrically connected. The first transistor is electrically connected to the first terminal, and the second transistor is electrically connected to the control terminal. By inputting a trigger voltage to the second transistor, the second transistor and the first switching member are conducted, which makes the first transistor become conductive. After the first transistor becoming conductive, the first transistor provides electricity to the second transistor to cause latching effect, and to consequently keep the first switching member conductive.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: A switch includes a first switching member and a latch circuit. A first terminal of the first switching member is electrically connected to a power source, while a second terminal thereof is electrically connected to a loading. The latch circuit includes a first transistor and a second transistor which are mutually electrically connected. The first transistor is electrically connected to the first terminal, and the second transistor is electrically connected to the control terminal. By inputting a trigger voltage to the second transistor, the second transistor and the first switching member are conducted, which makes the first transistor become conductive. After the first transistor becoming conductive, the first transistor provides electricity to the second transistor to cause latching effect, and to consequently keep the first switching member conductive.

Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact and a first gate structure. The first doped contact and the second doped contact are on the first doped region. The first doped contact and the second doped contact has a first PN junction therebetween. The first doped layer is under the first or second doped contact. The first doped layer and the first or second doped contact has a second PN junction therebetween. The second PN junction is adjoined with the first PN junction.

Abstract: In accordance with an embodiment, a high voltage switching and control circuit for an implantable medical device (IMD) is provided that comprises a high voltage positive (HVP) node configured to receive a positive high voltage signal from a high energy storage source; and a high voltage negative (HVN) node configured to receive a negative high voltage signal from a high energy storage source. First and second output terminals are configured to be connected to electrodes for delivering high voltage energy. First and second Silicon Controlled Rectifiers (SCR) switches are connected to the HVP node, the first and second SCR switches connected to the first and second output terminals respectively, wherein the first and second SCR switches each include a Darlington transistor pair having a first transistor stage joined to a second stage transistor at a common collector node.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device connected in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal connected to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, connected between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal connected to the control terminal; and a Zener diode, connected between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: Methods and techniques are disclosed for an intelligent GFCI device (IGFCI) having a microcontroller programmed to perform self-testing on a periodic basis and communicate the results of this testing to a remote monitoring device such as a remote central logging computer. In some implementations, with two-way (bidirectional) communication, a plurality of self-testing IGFCI devices can be tested and reset systematically from a remotely located device to reduce disruption to users. The IGFCI device can be configured to be automatically reset or manually reset upon the application of AC power to the device.

Abstract: A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

Abstract: A method by which contaminant (soot) content in Diesel engine oil is determined using electrical conductivity measurements of the Diesel oil at a high frequency, or by which contaminant (soot and/or water and/or anitfreeze) content is determined using the ratio of electrical conductivity measurements of the Diesel oil at a high frequency to the electrical conductivity measurements of the Diesel oil at a low frequency. Both the conductivity ratio and the high frequency conductivity are essentially independent of the brand of oil. High frequency is defined to be above 2 MHz whereas low frequency is defined to be D.C. to about 1 kHz.

Abstract: A bipolar junction transistor (BJT) used as a synchronous rectifier (SR) that is turned off by an active electronic device such as a transistor coupled between the base and collector of that SR BJT. The turn-off transistor functions to rapidly remove stored charge from the collector-base junction of the SR BJT when appropriate. Various active electronic devices are discussed as implementations of the turn-off transistor, including bipolar and field effect transistors of same or opposite polarity. Various anti-saturation and base current increasing circuits are also disclosed.

Abstract: A circuit arrangement, in particular for triggering an ignition output stage, having a power switching transistor and a switchable freewheeling circuit or an auxiliary channel. The freewheeling circuit or the auxiliary channel may be constituted by a triggerable four-layer element.

Abstract: The present invention relates to a normally-on bidirectional switch, including, in parallel between two power terminals of the switch, a first cathode-gate thyristor, the anode of which is connected to a first power terminal, a second anode-gate thyristor, the anode of which is connected to a second power terminal, and a resistor in series with a controllable switch, the midpoint of this series association being connected to the respective gates of the two thyristors. The present invention also provides a monolithic integration of the switch.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: The present invention relates to a component forming a normally on dual thyristor, which can be turned off by a voltage pulse on the control electrode, including a thyristor, a first depletion MOS transistor, the gate of which is connected to the source, connected between the anode gate and the cathode of the thyristor, and a second enhancement MOS transistor, the gate of which is connected to a control terminal.

Abstract: In an FET device having a pair of input terminals, a pair of output terminals, a plurality of FETs and driving circuits, the driving circuit has such a circuit structure that source electrodes of the FETs are electrically connected to each other. Each of gate electrodes of the FETs is independently connected to a photo-diode array. The gate electrodes of the FETs are not electrically short-circuited to each other. The FETs are tuned on and off in response to a single control signal.

Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.

Abstract: An electrostatic discharge protection circuit immune to latch-up during normal operation is disclosed. The ESD protection circuit is positioned at an IC pad for protecting an internal circuit within an integrated circuit from ESD damage. The electrostatic discharge protection circuit comprises a silicon-controlled rectifier and an ON/OFF controller. The silicon-controlled rectifier coupled between the IC pad and a grounding node to form an ESD path, wherein the ON/OFF controller is arranged in the conduction path. During normal operation the ON/OFF controller disconnects the ESD path so as to avoid latch-up even if noise interference happens.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: A birectional transistor switch for large signal voltages comprises a first (T1) and a second (T2) transistor arranged in series, which are supplied with base current under command of a control signal in order to short-circuit a signal terminal (ST) to a reference terminal (RT) which is connected to the substrate of the circuit. When the transistor switch is open large negative voltage excursions of the signal (U) on the signal terminal (ST) will fire a thyristor formed by the first transistor (T1) and a parasitic transistor (TP) and thus cause an undesired short-circuit between the signal terminal and the reference terminal (RT). This is prevented in that under these conditions the node (N) between the two transistors is short-circuited to the reference terminal (RT), as a result of which the loop gain in the thyristor becomes so small that this thyristor is no longer fired.

Abstract: The invention provides a silicon controlled rectifier having an anode and a cathode and including an NPN transistor and a PNP transistor. The NPN transistor has an emitter coupled to the cathode, a base and a collector. The PNP transistor has a base coupled to the NPN collector, an emitter coupled to the anode, a first collector coupled to the NPN base and a second collector coupled to the NPN collector.

Abstract: An electronic delay circuit (10) for use in a detonator (100) has a switching circuit (20) and a timer circuit (22). Switching circuit (20) controls the flow of a stored charge of electrical energy from a storage capacitor (12) to a bridge initiation element such as a semiconductor bridge (18) or a tungsten bridge. The timing of the release of this energy is controlled by timer circuit (22). Switching circuit (20) is an integrated, dielectrically isolated, bipolar CMOS (DI BiCMOS) circuit, whereas timer circuit (22) is a conventional CMOS circuit. The use of a DI BiCMOS switching circuit allows for greater efficiency of energy transfer from the storage capacitor (12) to the semiconductor bridge (18) than has previously been attained.

Abstract: A circuit for discharging of a photovoltaic power source has a first and a second terminal and the circuit comprises a discharge circuit which is connected between the first and second terminal of the power source which comprises a controllable current source which is controlled by a band gap reference.

Abstract: A driver circuit delays the turning on of a MOS transistor by utilizing the time-wise pattern of the circuit input signal rather than generating a delay within the circuit itself. A threshold type of circuit element is arranged so that no current flows toward or from, depending on the type of the MOS transistor, the control terminal before the voltage at the circuit input exceeds a predetermined value. This is achieved, for example, by coupling a Zener diode serially to the control terminal. Where the input signal is of a kind which increases with a degree of uniformity, the time required to exceed that threshold will correspond to the desired delay. Thus, the driver circuit can match the dynamic range of the input signal automatically.

Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.

Abstract: A high voltage switch in which an extended SCR is built in an insulated polysilicon layer for providing a single structure high voltage switch. The high voltage SCR is built by building unit SCRs comprising a cathode, a gate, an anode and a voltage sustaining area. The unit SCRs are built as horizontal linear devices. The unit SCRs can then be combined to form a large SCR by building each unit SCR so that the anode of one SCR is at least partially contiguous with the cathode of the next unit SCR.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.